Difference between revisions of "MBC1"

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__TOC__
 
__TOC__
  
−
Nintendo's MBC1 can be used to address up to 16 Mbit of ROM and 256 kbit of SRAM, depending on the mode MBC1 is set to.
+
Nintendo's MBC2 can be used to address up to 2 Mbit of ROM and has 512×4 bit of internal RAM.
  
 
= Pinout =
 
= Pinout =
  
−
[[Image:MBC1 Pinout.png|center|x300px]]
+
[[Image:MBC2 Pinout.png|center|x300px]]
  
 
{| class="wikitable pintable" style="margin:1em auto; width: 66%;"
 
{| class="wikitable pintable" style="margin:1em auto; width: 66%;"
Line 13: Line 13:
 
!style="width: 60%;" | Comment
 
!style="width: 60%;" | Comment
 
|-
 
|-
−
|24
+
|28
 
|VCC
 
|VCC
 
|PWR
 
|PWR
−
|5V supply
+
|I/O 5V supply
 
|-
 
|-
−
|12
+
|14
 
|GND
 
|GND
 
|PWR
 
|PWR
−
|Ground supply
+
|I/O Ground supply
 
|-
 
|-
−
|5{{ndash}}1
+
|21
−
|D4{{ndash}}D0
+
|VCC_RAM
−
|I
+
|PWR
 +
|RAM supply
 +
|-
 +
|7
 +
|GND_RAM
 +
|PWR
 +
|RAM Ground supply
 +
|-
 +
|12{{ndash}}9
 +
|D3{{ndash}}D0
 +
|I/O
 
|Data Bus
 
|Data Bus
 
|-
 
|-
−
|11
+
|1
 
|{{Overline|RD}}
 
|{{Overline|RD}}
 
|I
 
|I
 
|Low-Active Read Enable
 
|Low-Active Read Enable
 
|-
 
|-
−
|22
+
|27
 
|{{Overline|WR}}
 
|{{Overline|WR}}
 
|I
 
|I
 
|Low-Active Write Enable
 
|Low-Active Write Enable
 
|-
 
|-
−
|23
+
|26
 
|{{Overline|CS}}
 
|{{Overline|CS}}
 
|I
 
|I
 
|Low-Active Chip Select
 
|Low-Active Chip Select
 
|-
 
|-
−
|10
+
|15
 
|{{Overline|RESET}}
 
|{{Overline|RESET}}
 
|I
 
|I
 
|Low-Active Asynchronous Reset
 
|Low-Active Asynchronous Reset
 
|-
 
|-
−
|21{{ndash}}19
+
|20, 22, 23{{ndash}}25, 8, 6{{ndash}}2
−
|A15{{ndash}}A13
+
|A15{{ndash}}A14, A8{{ndash}}A0
 
|I
 
|I
 
|Address Bus
 
|Address Bus
 
|-
 
|-
−
|18{{ndash}}14
+
|16{{ndash}}19
−
|RA18{{ndash}}RA14
+
|RA17{{ndash}}RA14
 
|O
 
|O
 
|Upper ROM Address Lines
 
|Upper ROM Address Lines
−
|-
 
−
|7{{ndash}}6
 
−
|AA14{{ndash}}AA13
 
−
|O
 
−
|Upper ROM/RAM Address Lines
 
−
|-
 
−
|8
 
−
|{{Overline|RAM_CS}}
 
−
|O
 
−
|Low-Active RAM Chip Select
 
−
|-
 
−
|9
 
−
|RAM_CS
 
−
|O
 
−
|High-Active RAM Chip Select
 
 
|-
 
|-
 
|13
 
|13
Line 79: Line 74:
 
|}
 
|}
  
−
Footprint: SOP127P1200X225-24
+
Footprint: SOP127P1200X225-28
 +
 
 +
Remarks: All I/Os have diode protection against VCC/GND. Internal RAM is supplied by VCC as well as VCC_RAM, probably depending on the VCC voltage.
  
 
{{clear|both}}
 
{{clear|both}}
Line 88: Line 85:
 
Write-Accessible Registers:
 
Write-Accessible Registers:
  
−
* 0x0000-0x1FFF: RAM Enable register
+
* <tt>0b00-- ---0 ---- ----</tt>: RAM Enable register
−
* 0x2000-0x3FFF: ROM Bank register
+
* <tt>0b00-- ---1 ---- ----</tt>: ROM Bank register
−
* 0x4000-0x5FFF: RAM Bank register
+
* <tt>0b10-- ---a aaaa aaaa</tt>: Internal RAM
−
* 0x6000-0x7FFF: Mode register
 
  
 
== RAM Enable Register ==
 
== RAM Enable Register ==
Line 107: Line 103:
  
 
<pre>
 
<pre>
−
XX XX XX D4 D3 D2 D1 D0    0x00 @ reset
+
XX XX XX XX D3 D2 D1 D0    0x00 @ reset
−
        \____________/
+
            \_________/
 
                 \-------- ROM Bank
 
                 \-------- ROM Bank
  
 
</pre>
 
</pre>
  
−
ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA18{{ndash}}RA14.
+
ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA17{{ndash}}RA14.
−
 
 
−
== RAM Bank Register ==
 
−
 
 
−
<pre>
 
−
XX XX XX XX XX XX D1 D0    0x00 @ reset
 
−
                  \___/
 
−
                    \----- RAM Bank
 
−
 
 
−
</pre>
 
−
 
 
−
RAM Bank selects which bank is mapped to 0xA000-0xBFFF when in mode 4&nbsp;MBit/256&nbsp;kbit. When in mode 16&nbsp;Mbit/64&nbsp;kbit, it can be used to select the upper two ROM address lines.
 
−
 
 
−
== Mode Register ==
 
−
 
 
−
<pre>
 
−
XX XX XX XX XX XX XX D0    0x00 @ reset
 
−
                    \/
 
−
                      \--- Mode
 
−
 
 
−
</pre>
 
−
 
 
−
The mode bit switches between 16&nbsp;Mbit ROM/64&nbsp;kbit SRAM mode ('0') and 4&nbsp;Mbit ROM/256&nbsp;kbit SRAM mode ('1'). When in 16&nbsp;Mbit/64&nbsp;kbit mode, address lines AA14{{ndash}}AA13 switch according to A14. When in 4&nbsp;Mbit/256&nbsp;kbit mode, the upper address lines AA14{{ndash}}AA13 stay fixed regardless of A14.
 
  
 
= Behavior =
 
= Behavior =
  
 
<source lang="vhdl">
 
<source lang="vhdl">
−
library IEEE;
+
TODO
−
use IEEE.std_logic_1164.all;
 
−
 
 
−
entity MBC1 is
 
−
Port(
 
−
RESET_N  : in  std_logic;
 
−
RD_N    : in  std_logic;
 
−
WR_N    : in  std_logic;
 
−
CS_N    : in  std_logic;
 
−
A        : in  std_logic_vector(15 downto 13);
 
−
D        : in  std_logic_vector(4 downto 0);
 
−
RA      : out std_logic_vector(18 downto 14);
 
−
AA      : out std_logic_vector(14 downto 13);
 
−
ROM_CS_N : out std_logic;
 
−
RAM_CS_N : out std_logic;
 
−
RAM_CS  : out std_logic
 
−
);
 
−
end entity MBC1;
 
−
 
 
−
architecture Behavioral of MBC1 is
 
−
 
−
signal ram_enable_r : std_logic_vector(3 downto 0);
 
−
signal rom_bank_r  : std_logic_vector(4 downto 0);
 
−
signal ram_bank_r  : std_logic_vector(1 downto 0);
 
−
signal mode_r      : std_logic_vector(0 downto 0);
 
−
 
 
−
signal ram_enable_r_clk : std_logic;
 
−
signal rom_bank_r_clk  : std_logic;
 
−
signal ram_bank_r_clk  : std_logic;
 
−
signal mode_r_clk      : std_logic;
 
−
 
 
−
begin
 
−
 
 
−
-----------------------------------------------------------------------
 
−
-- Signal Assignments
 
−
-----------------------------------------------------------------------
 
−
 
 
−
ROM_CS_N <= '0' when ((A(15) = '0' and RD_N = '0') or RESET_N = '0') else
 
−
            '1';
 
−
 
 
−
RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A" and RESET_N = '1') else
 
−
            '1';
 
−
RAM_CS <= not RAM_CS_N;
 
−
 
 
−
RA(18 downto 14) <= "00000"    when (A(14) = '0' or RESET_N = '0') else
 
−
                    rom_bank_r when (rom_bank_r /= "00000") else
 
−
                    "00001";
 
−
 
 
−
AA(14 downto 13) <= "00" when (A(14) = '0' and mode_r = "0") else
 
−
                    ram_bank_r;
 
−
 
 
−
ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else
 
−
                    '1';
 
−
 
 
−
rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else
 
−
                  '1';
 
−
 
 
−
ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else
 
−
                  '1';
 
−
 
 
−
mode_r_clk <= '0' when (A = "011" and WR_N = '0') else
 
−
              '1';
 
−
 
 
−
-----------------------------------------------------------------------
 
−
-- Registers
 
−
-----------------------------------------------------------------------
 
−
 
 
−
ram_enable_p : process (
 
−
RESET_N,
 
−
ram_enable_r_clk
 
−
)
 
−
begin
 
−
 
 
−
if (RESET_N = '0') then
 
−
 
−
ram_enable_r <= x"0";
 
−
 
−
elsif (rising_edge(ram_enable_r_clk)) then
 
−
 
−
ram_enable_r <= D(3 downto 0);
 
−
 
−
end if;
 
−
 
 
−
end process ram_enable_p;
 
−
 
 
−
rom_bank_p : process (
 
−
RESET_N,
 
−
rom_bank_r_clk
 
−
)
 
−
begin
 
−
 
 
−
if (RESET_N = '0') then
 
−
 
−
rom_bank_r <= "00000";
 
−
 
−
elsif (rising_edge(rom_bank_r_clk)) then
 
−
 
−
rom_bank_r <= D;
 
−
 
−
end if;
 
−
 
−
end process rom_bank_p;
 
−
 
 
−
ram_bank_p : process (
 
−
RESET_N,
 
−
ram_bank_r_clk
 
−
)
 
−
begin
 
−
 
 
−
if (RESET_N = '0') then
 
−
 
−
ram_bank_r <= "00";
 
−
 
−
elsif (rising_edge(ram_bank_r_clk)) then
 
−
 
−
ram_bank_r <= D(1 downto 0);
 
−
 
−
end if;
 
−
 
−
end process ram_bank_p;
 
−
 
 
−
mode_p : process (
 
−
RESET_N,
 
−
mode_r_clk
 
−
)
 
−
begin
 
−
 
 
−
if (RESET_N = '0') then
 
−
 
−
mode_r <= "0";
 
−
 
−
elsif (rising_edge(mode_r_clk)) then
 
−
 
−
mode_r <= D(0 downto 0);
 
−
 
−
end if;
 
−
 
 
−
end process mode_p;
 
−
 
 
−
end architecture Behavioral;
 
 
</source>
 
</source>

Revision as of 03:03, 23 June 2015

Nintendo's MBC2 can be used to address up to 2 Mbit of ROM and has 512×4 bit of internal RAM.

Pinout

MBC2 Pinout.png
Pin No. Name Type Comment
28 VCC PWR I/O 5V supply
14 GND PWR I/O Ground supply
21 VCC_RAM PWR RAM supply
7 GND_RAM PWR RAM Ground supply
12Template:Ndash9 D3Template:NdashD0 I/O Data Bus
1 RD I Low-Active Read Enable
27 WR I Low-Active Write Enable
26 CS I Low-Active Chip Select
15 RESET I Low-Active Asynchronous Reset
20, 22, 23Template:Ndash25, 8, 6Template:Ndash2 A15Template:NdashA14, A8Template:NdashA0 I Address Bus
16Template:Ndash19 RA17Template:NdashRA14 O Upper ROM Address Lines
13 ROM_CS O Low-Active ROM Chip Select

Footprint: SOP127P1200X225-28

Remarks: All I/Os have diode protection against VCC/GND. Internal RAM is supplied by VCC as well as VCC_RAM, probably depending on the VCC voltage.

Registers

Write-Accessible Registers:

  • 0b00-- ---0 ---- ----: RAM Enable register
  • 0b00-- ---1 ---- ----: ROM Bank register
  • 0b10-- ---a aaaa aaaa: Internal RAM

RAM Enable Register

XX XX XX XX D3 D2 D1 D0    0x00 @ reset
            \_________/
                 \-------- RAM Enable

A value of 0x0A enables SRAM access, all other values disable SRAM access.

ROM Bank Register

XX XX XX XX D3 D2 D1 D0    0x00 @ reset
            \_________/
                 \-------- ROM Bank

ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA17Template:NdashRA14.

Behavior

TODO
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