Difference between revisions of "Game Boy Naming Convention"
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| Line 33: | Line 33: | ||
| B | | B | ||
| MBC1A/MBC1B/MBC1B1 | | MBC1A/MBC1B/MBC1B1 | ||
| − | | 512kbit | + | | 512kbit |
| -? | | -? | ||
| - | | - | ||
| Line 41: | Line 41: | ||
| 1Mbit | | 1Mbit | ||
| 64kbit | | 64kbit | ||
| − | | | + | | COB |
|- | |- | ||
| D | | D | ||
| MBC1A/MBC1B/MBC1B1 + CR1616 | | MBC1A/MBC1B/MBC1B1 + CR1616 | ||
| − | | 2Mbit | + | | 2Mbit |
| 256kbit | | 256kbit | ||
| - | | - | ||
| Line 74: | Line 74: | ||
|- | |- | ||
| K | | K | ||
| − | | MBC3A/MBC3B + CR2025 | + | | MBC3/MBC3A/MBC3B w/ X + CR2025 |
| + | | - | ||
| + | | - | ||
| + | | - | ||
| + | |- | ||
| + | | L | ||
| + | | MBC3/MBC3A/MBC3B w/o X + CR2025 | ||
| - | | - | ||
| - | | - | ||
| Line 80: | Line 86: | ||
|- | |- | ||
| M | | M | ||
| − | | MBC30 + CR2025 | + | | MBC30 w/ X + CR2025 |
| - | | - | ||
| - | | - | ||
| Line 89: | Line 95: | ||
| - | | - | ||
| - | | - | ||
| − | | | + | | SOP |
|- | |- | ||
| P | | P | ||
| Line 104: | Line 110: | ||
|- | |- | ||
| T | | T | ||
| − | | HuC1A + CR1616 | + | | HuC1/HuC1A + CR1616 |
| - | | - | ||
| - | | - | ||
| − | | | + | | TSOP I |
|- | |- | ||
| U | | U | ||
| Line 113: | Line 119: | ||
| - | | - | ||
| - | | - | ||
| − | | TSOP | + | | TSOP II |
|} | |} | ||
| Line 120: | Line 126: | ||
* 256kbit of ROM | * 256kbit of ROM | ||
* no SRAM | * no SRAM | ||
| − | * ROM chip package is a narrow SOIC | + | * ROM chip package is a narrow SOIC (SOP) |
| + | |||
| + | ROM and RAM sizes are maximum sizes, i.e. smaller memories will alias, while bigger memories will be inaccessible past the stated size. | ||
== PCB Revisions == | == PCB Revisions == | ||
| Line 133: | Line 141: | ||
*SP | *SP | ||
| − | Mostly minor routing differences if any. Sometimes additional components in 10, 20, SP. | + | Mostly minor routing differences if any. Sometimes additional components in 10, 20, SP. |
| + | First figure is major revision -- i.e. additional components, bigger changes -- while second figure is minor changes in masks only. | ||
== Optional Parts == | == Optional Parts == | ||
| Line 147: | Line 156: | ||
* DMG-DECN(K)-02 Mogurania (Mole Mania) | * DMG-DECN(K)-02 Mogurania (Mole Mania) | ||
| + | Working hypothesis: PCBs were made in Korea and to track failure rates, marked with (K)? | ||
= CGB PCB Naming Convention = | = CGB PCB Naming Convention = | ||
| Line 154: | Line 164: | ||
DMG-?NN-NN | DMG-?NN-NN | ||
||| \-- PCB revision | ||| \-- PCB revision | ||
| − | ||\----- PCB descriptor | + | ||\----- PCB descriptor RAM/ROM size combination |
| − | |\------ PCB descriptor | + | |\------ PCB descriptor MBC |
\------- PCB code | \------- PCB code | ||
Latest revision as of 12:58, 30 May 2016
Contents
DMG PCB Naming Convention
DMG PCB codes follow the following convention:
DMG[-?[?]]-???[?][(?)]-NN
| | | \-- PCB revision
| | \------- optional code in parentheses
| \-------------- mandatory three or four-letter descriptor
\--------------------- one or two-letter optional part
Descriptor Codes
| Code | MBC/Battery | ROM Size | RAM Size | ROM Package |
|---|---|---|---|---|
| (none) | - | - | - | QFP |
| A | none | 256kbit | none | - |
| B | MBC1A/MBC1B/MBC1B1 | 512kbit | -? | - |
| C | - | 1Mbit | 64kbit | COB |
| D | MBC1A/MBC1B/MBC1B1 + CR1616 | 2Mbit | 256kbit | - |
| E | - | 4Mbit | 512kbit | - |
| F | - | 8Mbit | - | - |
| G | MBC2A + CR1616 | 16Mbit | - | - |
| H | - | 32Mbit | - | - |
| K | MBC3/MBC3A/MBC3B w/ X + CR2025 | - | - | - |
| L | MBC3/MBC3A/MBC3B w/o X + CR2025 | - | - | - |
| M | MBC30 w/ X + CR2025 | - | - | - |
| N | - | - | - | SOP |
| P | MMM01 | - | - | - |
| S | MMM01 + CR1616 | - | - | - |
| T | HuC1/HuC1A + CR1616 | - | - | TSOP I |
| U | HuC3A + CR2025 | - | - | TSOP II |
For example, DMG-BEAN-02 is a PCB made for
- MBC1A/MBC1B/MBC1B1 (without battery)
- 256kbit of ROM
- no SRAM
- ROM chip package is a narrow SOIC (SOP)
ROM and RAM sizes are maximum sizes, i.e. smaller memories will alias, while bigger memories will be inaccessible past the stated size.
PCB Revisions
Numbers include
- 01
- 02
- 03
- 10
- 20
- SP
Mostly minor routing differences if any. Sometimes additional components in 10, 20, SP. First figure is major revision -- i.e. additional components, bigger changes -- while second figure is minor changes in masks only.
Optional Parts
- DMG-MC-SFCN-01 Momotarou Collection 2
- DMG-M-PEAN-10 Taito Variety Pack
MC = Momotarou Collection? MultiCart?
Code in parentheses after descriptor is only ever K.
- DMG-BEAN(K)-10 Xenon 2
- DMG-DECN(K)-02 Mogurania (Mole Mania)
Working hypothesis: PCBs were made in Korea and to track failure rates, marked with (K)?
CGB PCB Naming Convention
CGB PCB codes follow the following convention:
DMG-?NN-NN
||| \-- PCB revision
||\----- PCB descriptor RAM/ROM size combination
|\------ PCB descriptor MBC
\------- PCB code
PCB Code
- A: Production Cartridges
- B: Test Cartridges
- Z: Revisions of certain A?? variants. Sometimes routing changes.
PCB Descriptor
Descriptors describe MBC and ROM/RAM size combinations only.
| Number | MBC | RAM/ROM size combination | |
|---|---|---|---|
| RAM sizes | ROM sizes | ||
| 0 | MBC5 (w/ or w/o rumble) | 4/8M | 2/4k EEPROM or 1M SRAM |
| 1 | MBC5 (w/ rumble) | 16/32/64M | 64k |
| 2 | G-MMC1 (+ 8M FLASH) | 2/4/8M | 256k |
| 3 | MBC6 (+ 8M FLASH) | 16/32/64M | 256k |
| 4 | MBC7 | 4/8M | -? |
| 5 | - | -? | -? |
| 6 | - | 2/4/8M | 64k |
| 7 | - | 16/32M | 2/4k EEPROM |
| 8 | - | -? | -? |
| 9 | - | -? | -? |
Maybe actually hierarchy? I.e. second figure is sub-index in first figure MBC PCB designs?
PCB Revisions
Numbers include
- 01
- 10
Never observed any major differences. Maybe minor solder mask differences?
