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| − | Several Sachen Mappers are thought to exist.
| + | __TOC__ |
| | + | |
| | + | Sachen manufactured unlicensed Game Boy and Game Boy Color games from ~2000 until 2007. |
| | + | |
| | + | Two Sachen Mappers are thought to exist. Both exist in a stand-alone variant -- just the mapper under glob top -- and an integrated variant -- mapper and ROM are under the same glob top on the PCB. |
| | | | |
| | {| class="wikitable" style="width: 30%;" | | {| class="wikitable" style="width: 30%;" |
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| | !style="width: 50%;" | Comment | | !style="width: 50%;" | Comment |
| | |- | | |- |
| − | |Sachen MMC1 | + | |[[Sachen MMC1]] |
| | |MMC for mono 4B games. | | |MMC for mono 4B games. |
| | |- | | |- |
| − | |Sachen MMC2 | + | |[[Sachen MMC2]] |
| | |MMC for mono/color 1B games. | | |MMC for mono/color 1B games. |
| | | | |
| | MMC for color 4B games. | | MMC for color 4B games. |
| | | | |
| − | MMC for color 6B games. (?) | + | MMC for color 6B games. |
| | | | |
| | MMC for color 8B games. | | MMC for color 8B games. |
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| | |} | | |} |
| | | | |
| − | = Sachen MMC1 = | + | = Notes = |
| − | | |
| − | 4B-005 on TG-002, 4B-005 on 1231 and 4B-007 on SA-111 tested.
| |
| − | | |
| − | Write-Accessible Registers:
| |
| − | | |
| − | * <tt>0x0000-0x1FFF</tt>: Base ROM bank register
| |
| − | * <tt>0x2000-0x3FFF</tt>: ROM bank register
| |
| − | * <tt>0x4000-0x5FFF</tt>: ROM bank mask register
| |
| − | | |
| − | Memory Map:
| |
| − | | |
| − | * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0
| |
| − | * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank
| |
| − | * <tt>0x8000-0xBFFF</tt>: Mapped ROM bank #0
| |
| − | * <tt>0xC000-0xFFFF</tt>: Mapped Switchable ROM bank
| |
| − | | |
| − | Mapped here means adjusted for absolute Base ROM bank.
| |
| − | | |
| − | Keep in mind that region 0x8000-0xFFFF being mapped to ROM just means that the RAn pins depend solely on A14.
| |
| − | | |
| − | == Modes of Operation ==
| |
| − | | |
| − | Sachen MMC1 has two modes of operation ''locked'' and ''unlocked''. It defaults to ''locked'' after reset.
| |
| − | | |
| − | This is used to display the Sachen logo instead of the Nintendo logo for the DMG bootstrap ROM. While ''locked'', the mapper will keep RA7 set.
| |
| − | | |
| − | The unlock sequence is 0x31 transitions of A15 from high to low. Starting on the last transition, RA7 will follow A7. All control signals are don't cares for this.
| |
| − | | |
| − | Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''
| |
| − | | |
| − | The only way to ''lock'' the mapper after ''unlocking'' is to reset it.
| |
| − | | |
| − | == Multi Memory Remap ==
| |
| − | | |
| − | Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.
| |
| − | | |
| − | The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre>
| |
| − | | |
| − | == Header Scramble ==
| |
| − | | |
| − | Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:
| |
| − | | |
| − | <pre>
| |
| − | RA0 <= A6
| |
| − | RA1 <= A4
| |
| − | RA4 <= A1
| |
| − | RA6 <= A0
| |
| − | </pre>
| |
| − | | |
| − | When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.
| |
| − | | |
| − | == ROM Bank Register ==
| |
| − | | |
| − | The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.
| |
| − | | |
| − | <pre>
| |
| − | D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset
| |
| − | \_____________________/
| |
| − | \___/ \-------- ROM Bank
| |
| − | |
| |
| − | \----------------- Map Enable
| |
| − | </pre>
| |
| − | | |
| − | ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.
| |
| − | Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.
| |
| − | | |
| − | The width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.
| |
| − | | |
| − | == Base ROM Bank Register ==
| |
| − | | |
| − | This register stores the base ROM bank.
| |
| − | | |
| − | <pre>
| |
| − | D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset
| |
| − | \_____________________/
| |
| − | \-------- Base ROM Bank
| |
| − | </pre>
| |
| − | | |
| − | This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.
| |
| − | Changes to this register take immediate effect.
| |
| − | | |
| − | == ROM bank mask register ==
| |
| − | | |
| − | | |
| − | This register stores the ROM bank mask.
| |
| − | | |
| − | <pre>
| |
| − | D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset
| |
| − | \_____________________/
| |
| − | \-------- ROM Bank Mask
| |
| − | </pre>
| |
| − | | |
| − | This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.
| |
| − | Changes to this register take immediate effect.
| |
| − | | |
| − | = Sachen MMC2 =
| |
| − | | |
| − | 4B-007 on SA-113 and 1B-001/1B-005/31B-001 on SA8MBT6-2 (w/ and w/o BAT) tested.
| |
| − | | |
| − | Write-Accessible Registers:
| |
| − | | |
| − | * <tt>0x0000-0x1FFF</tt>: Base ROM bank register
| |
| − | * <tt>0x2000-0x3FFF</tt>: ROM bank register
| |
| − | * <tt>0x4000-0x5FFF</tt>: ROM bank mask register
| |
| − | | |
| − | Memory Map:
| |
| − | | |
| − | * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0
| |
| − | * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank
| |
| − | * <tt>0x8000-0xBFFF</tt>: Mapped ROM bank #0
| |
| − | * <tt>0xC000-0xFFFF</tt>: Mapped Switchable ROM bank
| |
| − | | |
| − | Mapped here means adjusted for absolute Base ROM bank.
| |
| − | | |
| − | Keep in mind that region 0x8000-0xFFFF being mapped to ROM just means that the RAn pins depend solely on A14.
| |
| − | | |
| − | == Modes of Operation ==
| |
| − | | |
| − | Sachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.
| |
| − | | |
| − | This is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.
| |
| − | | |
| − | While in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.
| |
| − | | |
| − | The unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.
| |
| − | Going from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.
| |
| − | The MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.
| |
| − | | |
| − | Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.
| |
| − | | |
| − | The only way to ''lock'' the mapper after ''unlocking'' is to reset it.
| |
| − | | |
| − | == Multi Memory Remap ==
| |
| − | | |
| − | Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.
| |
| − | | |
| − | The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre>
| |
| − | | |
| − | == Header Scramble ==
| |
| − | | |
| − | Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:
| |
| − | | |
| − | <pre>
| |
| − | RA0 <= A6
| |
| − | RA1 <= A4
| |
| − | RA4 <= A1
| |
| − | RA6 <= A0
| |
| − | </pre>
| |
| − | | |
| − | When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.
| |
| − | | |
| − | == ROM Bank Register ==
| |
| − | | |
| − | The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.
| |
| − | | |
| − | <pre>
| |
| − | D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset
| |
| − | \_____________________/
| |
| − | \___/ \-------- ROM Bank
| |
| − | |
| |
| − | \----------------- Map Enable
| |
| − | </pre>
| |
| − | | |
| − | ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.
| |
| − | Map Enable bits are used to enable write access to the [[#Base ROM Bank Register_2|#Base ROM Bank Register]] and [[#ROM bank mask register_2|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.
| |
| − | | |
| − | The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.
| |
| − | | |
| − | == Base ROM Bank Register ==
| |
| − | | |
| − | This register stores the base ROM bank.
| |
| − | | |
| − | <pre>
| |
| − | D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset
| |
| − | \_____________________/
| |
| − | \-------- Base ROM Bank
| |
| − | </pre>
| |
| − | | |
| − | This register is writable without limitation when Map Enable in the [[#ROM Bank Register_2|#ROM Bank Register]] is 0b11.
| |
| − | Changes to this register take immediate effect.
| |
| − | | |
| − | == ROM bank mask register ==
| |
| − | | |
| − | | |
| − | This register stores the ROM bank mask.
| |
| − | | |
| − | <pre>
| |
| − | D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset
| |
| − | \_____________________/
| |
| − | \-------- ROM Bank Mask
| |
| − | </pre>
| |
| − | | |
| − | This register is writable without limitation when Map Enable in the [[#ROM Bank Register_2|#ROM Bank Register]] is 0b11.
| |
| − | Changes to this register take immediate effect.
| |
| − | | |
| − | = MMC1/MMC2 Notes =
| |
| | | | |
| | == 0x6000 - 0x7FFF == | | == 0x6000 - 0x7FFF == |
Sachen manufactured unlicensed Game Boy and Game Boy Color games from ~2000 until 2007.
Two Sachen Mappers are thought to exist. Both exist in a stand-alone variant -- just the mapper under glob top -- and an integrated variant -- mapper and ROM are under the same glob top on the PCB.
| Name
|
Comment
|
| Sachen MMC1
|
MMC for mono 4B games.
|
| Sachen MMC2
|
MMC for mono/color 1B games.
MMC for color 4B games.
MMC for color 6B games.
MMC for color 8B games.
MMC for color 16B games.
MMC for color 31B games.
|
Notes
0x6000 - 0x7FFF
Writing to the 0x6000-0x7FFF range did not affect mapping in any way. I did an exhaustive test.
for (k= 0x0000; k < 0x2000; k++) {
for (l = 0x00; l < 0x100u; l++) {
// reset to base RB 0x00 with mask 0x00 here
// map RB 0x04 with mask 0xFC
writeb(0x2000u, 0xFFu); // enable map regs
writeb(0x0000u, 0x04u); // base RB
writeb(0x4000u, 0xFCu); // mask
writeb(0x6000 | k, l); // see if this does anything
writeb(0x2000u, 0x00u); // disable map regs
//check RB 0x00 - RB 0x04 against known hashes and report error
}
}
0xA000 - 0xBFFF
Reading from this range produced no results.
Miscellaneous Information
Too bad Sachen screwed up (on 4B-007 at least) and actually writes the base RB to the mask register and the mask to the base RB register, thus all games having broken masking. But due to power-of-2 sizes of RBs and masks, it turns out that only a few extra RBs are mappable which shouldn't be instead of the games skipping ROM banks.
I noticed that the Sachen logo check -- VRAM comparison of Sachen logo starting at 0x8010 -- was disabled in the mapped games. I also noticed that games do write to 0x0000-0x1FFF while being mapped, so this may have some effect. Technically, since A15..A6, A4, A1, A0 are connected, there might be many registers mapped. Initial tests show this not to be the case.
