Sachen Mappers - Revision history

Tauwasser: split pages up

2018-02-15T22:50:42Z

split pages up

Show changes

Tauwasser: yep, 6B-001 is on SA8MBT6-2

2016-02-10T00:21:06Z

yep, 6B-001 is on SA8MBT6-2

Tauwasser: move TOC

2015-12-10T19:48:39Z

move TOC

Tauwasser: / Register / same width for all address ranges

2015-08-02T18:34:49Z

/ Register / same width for all address ranges

Tauwasser: 1231 pads aren't bonded, so it's still not 100% confirmed. But why have the pads in the right place then?

2015-04-11T19:59:53Z

1231 pads aren't bonded, so it's still not 100% confirmed. But why have the pads in the right place then?

Tauwasser: add reset values for all registers; verified on 1231 and SA8MBT6-2 w/o BAT

2015-04-11T19:58:27Z

add reset values for all registers; verified on 1231 and SA8MBT6-2 w/o BAT

Tauwasser: Update MMC1: it does have eight high address lines, as seen on PCB 1231 (six visible, two more pads, 15 marked traces on PCB with 13 traces visible)

2015-03-10T19:24:12Z

Update MMC1: it does have eight high address lines, as seen on PCB 1231 (six visible, two more pads, 15 marked traces on PCB with 13 traces visible)

Tauwasser: /* ROM bank mask register */ fix links

2015-01-29T01:24:25Z

‎ROM bank mask register: fix links

Tauwasser: /* Base ROM Bank Register */ fix links

2015-01-29T01:23:59Z

‎Base ROM Bank Register: fix links

Tauwasser: /* ROM Bank Register */ fix links

2015-01-29T01:23:31Z

‎ROM Bank Register: fix links

@@ Line 15: / Line 15: @@
 MMC for color 4B games.
-MMC for color 6B games. (?)
+MMC for color 6B games.
 MMC for color 8B games.

← Older revision		Revision as of 19:48, 10 December 2015
Line 1:		Line 1:
		+	__TOC__
		+
	Several Sachen Mappers are thought to exist.		Several Sachen Mappers are thought to exist.

@@ Line 28: / Line 28: @@
 Write-Accessible Registers:
-* 0x0000-0x1FFF: Base ROM bank register
+* <tt>0x0000-0x1FFF</tt>: Base ROM bank register
-* 0x2000-0x3FFF: ROM bank register
+* <tt>0x2000-0x3FFF</tt>: ROM bank register
-* 0x4000-0x5FFF: ROM bank mask register
+* <tt>0x4000-0x5FFF</tt>: ROM bank mask register
 Memory Map:
-* 0x0000-0x3FFF: Mapped ROM bank #0
+* <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0
-* 0x4000-0x7FFF: Mapped Switchable ROM bank
+* <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank
-* 0x8000-0xBFFF: Mapped ROM bank #0
+* <tt>0x8000-0xBFFF</tt>: Mapped ROM bank #0
-* 0xC000-0xFFFF: Mapped Switchable ROM bank
+* <tt>0xC000-0xFFFF</tt>: Mapped Switchable ROM bank
 Mapped here means adjusted for absolute Base ROM bank.
@@ Line 124: / Line 124: @@
 Write-Accessible Registers:
-* 0x0000-0x1FFF: Base ROM bank register
+* <tt>0x0000-0x1FFF</tt>: Base ROM bank register
-* 0x2000-0x3FFF: ROM bank register
+* <tt>0x2000-0x3FFF</tt>: ROM bank register
-* 0x4000-0x5FFF: ROM bank mask register
+* <tt>0x4000-0x5FFF</tt>: ROM bank mask register
 Memory Map:
-* 0x0000-0x3FFF: Mapped ROM bank #0
+* <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0
-* 0x4000-0x7FFF: Mapped Switchable ROM bank
+* <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank
-* 0x8000-0xBFFF: Mapped ROM bank #0
+* <tt>0x8000-0xBFFF</tt>: Mapped ROM bank #0
-* 0xC000-0xFFFF: Mapped Switchable ROM bank
+* <tt>0xC000-0xFFFF</tt>: Mapped Switchable ROM bank
 Mapped here means adjusted for absolute Base ROM bank.

@@ Line 89: / Line 89: @@
 Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.
-The width of this register is based off the fact that there are six high address lines, two more landing pads visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.
+The width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.
 == Base ROM Bank Register ==

@@ Line 79: / Line 79: @@
 <pre>
-D7 D6 D5 D4 D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0    0x01 @ reset
 \_____________________/
        \___/      \-------- ROM Bank
@@ Line 96: / Line 96: @@
 <pre>
-D7 D6 D5 D4 D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0    0x00 @ reset
 \_____________________/
                   \-------- Base ROM Bank
@@ Line 110: / Line 110: @@
 <pre>
-D7 D6 D5 D4 D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0    0x00 @ reset
 \_____________________/
                   \-------- ROM Bank Mask
@@ Line 179: / Line 179: @@
 <pre>
-D7 D6 D5 D4 D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0    0x01 @ reset
 \_____________________/
        \___/      \-------- ROM Bank
@@ Line 196: / Line 196: @@
 <pre>
-D7 D6 D5 D4 D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0    0x00 @ reset
 \_____________________/
                   \-------- Base ROM Bank
@@ Line 210: / Line 210: @@
 <pre>
-D7 D6 D5 D4 D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0    0x00 @ reset
 \_____________________/
                   \-------- ROM Bank Mask

@@ Line 24: / Line 24: @@
 = Sachen MMC1 =
-B-005 on TG-002 and 4B-007 on SA-111 tested.
+B-005 on TG-002, 4B-005 on 1231 and 4B-007 on SA-111 tested.
 Write-Accessible Registers:
@@ Line 76: / Line 76: @@
 == ROM Bank Register ==
-The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. However, only D5..D0 are seemingly used. This means, that ROM Bank 0x00 can be mapped to 0x4000-0x7FFF by abusing the overflow in this register.
+The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.
 <pre>
-XX XX D5 D4 D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0
-       \___/ \_________/
+\_____________________/
-        |        \-------- ROM Bank
+       \___/      \-------- ROM Bank
          \----------------- Map Enable
 </pre>
@@ Line 88: / Line 89: @@
 Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.
-The width of this register is based off the fact that there are only four high address lines on the TB-002 PCB. The Map Enable bits were not observed to have any effect on mapping.
+The width of this register is based off the fact that there are six high address lines, two more landing pads visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.
 == Base ROM Bank Register ==
@@ Line 95: / Line 96: @@
 <pre>
-XX XX XX XX D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0
-            \_________/
+\_____________________/
                   \-------- Base ROM Bank
 </pre>
@@ Line 102: / Line 103: @@
 This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.
 Changes to this register take immediate effect.
 == ROM bank mask register ==
@@ Line 110: / Line 110: @@
 <pre>
-XX XX XX XX D3 D2 D1 D0
+D7 D6 D5 D4 D3 D2 D1 D0
-            \_________/
+\_____________________/
                   \-------- ROM Bank Mask
 </pre>
@@ Line 117: / Line 117: @@
 This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.
 Changes to this register take immediate effect.
 = Sachen MMC2 =

@@ Line 188: / Line 188: @@
 ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.
-Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.
+Map Enable bits are used to enable write access to the [[#Base ROM Bank Register_2|#Base ROM Bank Register]] and [[#ROM bank mask register_2|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.
 The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.