Sachen MMC1 - Revision history

Tauwasser: Categorize into DMG as this page is apparently hard to find.

2021-08-19T20:34:14Z

Categorize into DMG as this page is apparently hard to find.

Tauwasser: /* Pinouts */

2018-08-23T14:47:35Z

‎Pinouts

Tauwasser: /* Behavior */

2018-08-23T14:26:32Z

‎Behavior

Tauwasser: /* Pinouts */

2018-08-23T14:22:40Z

‎Pinouts

Tauwasser: split into own page

2018-02-15T22:26:58Z

split into own page

New page

Sachen's MMC1 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.

= Pinout =

= Theory of Operation =

Sachen's MMC1 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.
To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.

== Modes of Operation ==

Sachen MMC1 has two modes of operation ''locked'' and ''unlocked''. It defaults to ''locked'' after reset.

This is used to display the Sachen logo instead of the Nintendo logo for the DMG bootstrap ROM. While ''locked'', the mapper will keep RA7 set.

The unlock sequence is 0x31 transitions of A15 from high to low. Starting on the last transition, RA7 will follow A7. All control signals are don't cares for this.

Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''

The only way to ''lock'' the mapper after ''unlocking'' is to reset it.

== Header Scramble ==

Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:

<pre>
RA0 <= A6
RA1 <= A4
RA4 <= A1
RA6 <= A0
</pre>

When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.

== Multi Memory Remap ==

Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.

The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre>

= Memory Map =

* <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0
* <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank
* <tt>0x8000-0xFFFF</tt>: Unmapped

Mapped here means adjusted for absolute Base ROM bank.

The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.

= Registers =

Write-Accessible Registers:

* <tt>0x0000-0x1FFF</tt>: Base ROM bank register
* <tt>0x2000-0x3FFF</tt>: ROM bank register
* <tt>0x4000-0x5FFF</tt>: ROM bank mask register

== ROM Bank Register ==

The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.

<pre>
D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset
\_____________________/
\___/ \-------- ROM Bank
|
\----------------- Map Enable
</pre>

ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.
Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.

The width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.

== Base ROM Bank Register ==

This register stores the base ROM bank.

<pre>
D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset
\_____________________/
\-------- Base ROM Bank
</pre>

This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.
Changes to this register take immediate effect.

== ROM bank mask register ==

This register stores the ROM bank mask.

<pre>
D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset
\_____________________/
\-------- ROM Bank Mask
</pre>

This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.
Changes to this register take immediate effect.

= Behavior =

← Older revision		Revision as of 20:34, 19 August 2021
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	The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.		The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.
	Depending on the bonded ROM smaller ROMs may have an additional low-active CE line on RA17 or RA18.		Depending on the bonded ROM smaller ROMs may have an additional low-active CE line on RA17 or RA18.
		+
		+	[[Category:DMG]]

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 |O
 |Upper ROM Address Lines
 |}

← Older revision		Revision as of 14:26, 23 August 2018
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	= Behavior =		= Behavior =
		+
		+	== Integrated ROM ==
		+
		+	The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.
		+	Depending on the bonded ROM smaller ROMs may have an additional low-active CE line on RA17 or RA18.

@@ Line 1: / Line 1: @@
 Sachen's MMC1 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.
-= Pinout =
+= Pinouts =
 = Theory of Operation =