MBC2 - Revision history

Tauwasser: I/O supply pins also supply core logic

2017-06-09T04:21:59Z

I/O supply pins also supply core logic

Tauwasser: /* Behavior */ fix syntax error, fix rising_edge compound argument

2016-10-26T22:13:38Z

‎Behavior: fix syntax error, fix rising_edge compound argument

Tauwasser: some explanation for VHDL

2016-04-10T18:28:57Z

some explanation for VHDL

Tauwasser: remove ndash template (some bullshit parsing error)

2015-08-02T17:29:32Z

remove ndash template (some bullshit parsing error)

Tauwasser: /* Registers */

2015-08-02T15:37:05Z

‎Registers

Tauwasser: /* Behavior */ forgot to invert when switching from boolean logic to binary logic

2015-08-02T11:25:00Z

‎Behavior: forgot to invert when switching from boolean logic to binary logic

Tauwasser: /* Behavior */ add behavioral model

2015-08-02T11:00:05Z

‎Behavior: add behavioral model

Tauwasser: recat DMG

2015-06-23T01:34:04Z

recat DMG

Tauwasser: Initial Revision :)

2015-06-23T01:26:22Z

Initial Revision :)

New page

__TOC__

Nintendo's MBC2 can be used to address up to 2 Mbit of ROM and 512×4 bit of internal RAM.

= Pinout =

[[Image:MBC2 Pinout.png|center|x300px]]

{| class="wikitable pintable" style="margin:1em auto; width: 66%;"
!style="width: 10%;" | Pin No.
!style="width: 20%;" | Name
!style="width: 10%;" | Type
!style="width: 60%;" | Comment
|-
|28
|VCC
|PWR
|I/O 5V supply
|-
|14
|GND
|PWR
|I/O Ground supply
|-
|21
|VCC_RAM
|PWR
|RAM supply
|-
|7
|GND_RAM
|PWR
|RAM Ground supply
|-
|12{{ndash}}9
|D3{{ndash}}D0
|I/O
|Data Bus
|-
|1
|{{Overline|RD}}
|I
|Low-Active Read Enable
|-
|27
|{{Overline|WR}}
|I
|Low-Active Write Enable
|-
|26
|{{Overline|CS}}
|I
|Low-Active Chip Select
|-
|15
|{{Overline|RESET}}
|I
|Low-Active Asynchronous Reset
|-
|20, 22{{ndash}}25, 8, 6{{ndash}}2
|A15{{ndash}}A14, A8{{ndash}}A0
|I
|Address Bus
|-
|16{{ndash}}19
|RA17{{ndash}}RA14
|O
|Upper ROM Address Lines
|-
|13
|{{Overline|ROM_CS}}
|O
|Low-Active ROM Chip Select
|}

Footprint: SOP127P1200X225-24

Remarks: All I/O pins are protected via diodes to VCC/GND. VCC and VCC_RAM both supply RAM -- probably depending on VCC voltage.

{{clear|both}}

= Registers =

Write-Accessible Registers:

* <tt>0b00-- ---0 ---- ----</tt>: RAM Enable register
* <tt>0b00-- ---1 ---- ----</tt>: ROM Bank register
* <tt>0b10-- ---a aaaa aaaa</tt>: Internal RAM

== RAM Enable Register ==

<pre>
XX XX XX XX D3 D2 D1 D0 0x00 @ reset
\_________/
\-------- RAM Enable

</pre>

A value of 0x0A enables RAM access, all other values disable RAM access.

== ROM Bank Register ==

<pre>
XX XX XX XX D3 D2 D1 D0 0x00 @ reset
\_________/
\-------- ROM Bank

</pre>

ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA17{{ndash}}RA14.

= Behavior =

<source lang="vhdl">
TODO
</source>

@@ Line 120: / Line 120: @@
 library IEEE;
 use IEEE.std_logic_1164.all;
 entity MBC2 is
@@ Line 131: / Line 132: @@
 		D        : inout std_logic_vector(3 downto 0);
 		RA       : out   std_logic_vector(17 downto 14);
-		ROM_CS_N : out   std_logic;
+		ROM_CS_N : out   std_logic
 	);
 end entity MBC2;
@@ Line 146: / Line 147: @@
 signal ram_enable_r_clk : std_logic;
 signal rom_bank_r_clk   : std_logic;
 signal ram_cs_n : std_logic;
@@ Line 183: / Line 185: @@
 rom_bank_r_clk <= '0' when (A_HI_int = "00" and A_int(8) = '1' and WR_N_int = '0') else
                    '1';
 -----------------------------------------------------------------------
@@ Line 229: / Line 233: @@
 	WR_N_int,
 	RD_N_int,
-	ram_cs_n
+	ram_cs_n,
+	)
 begin
@@ Line 246: / Line 251: @@
 	-- write
-	if (rising_edge(not RD_N_int or WR_N_int or ram_cs_n)) then
+	if (rising_edge(ram_clk)) then
 		ram(to_integer(unsigned(A_int))) <= D;

← Older revision		Revision as of 18:28, 10 April 2016
Line 113:		Line 113:

	= Behavior =		= Behavior =
		+
		+	When both {{Overline\|RD}} and {{Overline\|WR}} are low, MBC2 will drive 0x00 on D3..D0. The same is true for the reset state ({{Overline\|RESET}} asserted). Therefore I modeled the behavior as belonging to the internal SRAM.
		+	There might be a power-up bug with MBC2. Many games do not make use of 0xA000, maybe because there really is a problem at reset.

	<source lang="vhdl">		<source lang="vhdl">

@@ Line 241: / Line 241: @@
 	-- write
-	if (rising_edge(not RD_N_int and WR_N_int and ram_cs_n)) then
+	if (rising_edge(not RD_N_int or WR_N_int or ram_cs_n)) then
 		ram(to_integer(unsigned(A_int))) <= D;

@@ Line 113: / Line 113: @@
 <source lang="vhdl">
-TODO
+library IEEE;
 </source>
 [[Category:DMG]]

← Older revision		Revision as of 01:34, 23 June 2015
Line 115:		Line 115:
	TODO		TODO
	</source>		</source>
		+
		+	[[Category:DMG]]

@@ Line 16: / Line 16: @@
 |VCC
 |PWR
-|I/O 5V supply
+|I/O + logic 5V supply
 |-
 |14
 |GND
 |PWR
-|I/O Ground supply
+|I/O + logic Ground supply
 |-
 |21

@@ Line 33: / Line 33: @@
 |RAM Ground supply
 |-
-|12{{ndash}}9
+|12&ndash;9
-|D3{{ndash}}D0
+|D3&ndash;D0
 |I/O
 |Data Bus
@@ Line 58: / Line 58: @@
 |Low-Active Asynchronous Reset
 |-
-|20, 22{{ndash}}25, 8, 6{{ndash}}2
+|20, 22&ndash;25, 8, 6&ndash;2
-|A15{{ndash}}A14, A8{{ndash}}A0
+|A15&ndash;A14, A8&ndash;A0
 |I
 |Address Bus
 |-
-|16{{ndash}}19
+|16&ndash;19
-|RA17{{ndash}}RA14
+|RA17&ndash;RA14
 |O
 |Upper ROM Address Lines
@@ Line 110: / Line 110: @@
 </pre>
-ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA17{{ndash}}RA14.
+ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA17&ndash;RA14.
 = Behavior =

@@ Line 86: / Line 86: @@
 * <tt>0b00-- ---0 ---- ----</tt>: RAM Enable register
 * <tt>0b00-- ---1 ---- ----</tt>: ROM Bank register
 * <tt>0b10-- ---a aaaa aaaa</tt>: Internal RAM