MBC1 - Revision history

Tauwasser: /* Mode Register */

2017-06-23T20:30:31Z

‎Mode Register

2017-06-22T19:20:43Z

Removed superfluous RESET_N check in RAM_CS_N. RESET_N asynchronously resets ram_enable_r anyway.

2015-08-02T18:33:06Z

‎Registers: same width for all address ranges

2015-08-02T17:29:01Z

remove ndash template (some bullshit parsing error)

2015-06-23T01:33:49Z

recat DMG

2015-06-23T01:28:11Z

Undo revision 74 by Tauwasser (talk) Whoops

2015-06-23T01:03:13Z

2015-05-27T18:47:29Z

‎Pinout: silly me

2015-05-27T01:31:50Z

‎Pinout: add footprint information :)

2015-05-27T01:04:43Z

‎Behavior: use source for highlighting

@@ Line 130: / Line 130: @@
 <pre>
 XX XX XX XX XX XX XX D0    0x00 @ reset
-                     \/
                        \--- Mode

@@ Line 180: / Line 180: @@
              '1';
-RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A" and RESET_N = '1') else
+RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else
              '1';
 RAM_CS <= not RAM_CS_N;

@@ Line 88: / Line 88: @@
 Write-Accessible Registers:
-* 0x0000-0x1FFF: RAM Enable register
+* <tt>0x0000-0x1FFF</tt>: RAM Enable register
-* 0x2000-0x3FFF: ROM Bank register
+* <tt>0x2000-0x3FFF</tt>: ROM Bank register
-* 0x4000-0x5FFF: RAM Bank register
+* <tt>0x4000-0x5FFF</tt>: RAM Bank register
-* 0x6000-0x7FFF: Mode register
+* <tt>0x6000-0x7FFF</tt>: Mode register
 == RAM Enable Register ==

@@ Line 23: / Line 23: @@
 |Ground supply
 |-
-|5{{ndash}}1
+|5&ndash;1
-|D4{{ndash}}D0
+|D4&ndash;D0
 |I
 |Data Bus
@@ Line 48: / Line 48: @@
 |Low-Active Asynchronous Reset
 |-
-|21{{ndash}}19
+|21&ndash;19
-|A15{{ndash}}A13
+|A15&ndash;A13
 |I
 |Address Bus
 |-
-|18{{ndash}}14
+|18&ndash;14
-|RA18{{ndash}}RA14
+|RA18&ndash;RA14
 |O
 |Upper ROM Address Lines
 |-
-|7{{ndash}}6
+|7&ndash;6
-|AA14{{ndash}}AA13
+|AA14&ndash;AA13
 |O
 |Upper ROM/RAM Address Lines
@@ Line 113: / Line 113: @@
 </pre>
-ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA18{{ndash}}RA14.
+ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA18&ndash;RA14.
 == RAM Bank Register ==
@@ Line 135: / Line 135: @@
 </pre>
-The mode bit switches between 16&nbsp;Mbit ROM/64&nbsp;kbit SRAM mode ('0') and 4&nbsp;Mbit ROM/256&nbsp;kbit SRAM mode ('1'). When in 16&nbsp;Mbit/64&nbsp;kbit mode, address lines AA14{{ndash}}AA13 switch according to A14. When in 4&nbsp;Mbit/256&nbsp;kbit mode, the upper address lines AA14{{ndash}}AA13 stay fixed regardless of A14.
+The mode bit switches between 16&nbsp;Mbit ROM/64&nbsp;kbit SRAM mode ('0') and 4&nbsp;Mbit ROM/256&nbsp;kbit SRAM mode ('1'). When in 16&nbsp;Mbit/64&nbsp;kbit mode, address lines AA14&ndash;AA13 switch according to A14. When in 4&nbsp;Mbit/256&nbsp;kbit mode, the upper address lines AA14&ndash;AA13 stay fixed regardless of A14.
 = Behavior =

← Older revision		Revision as of 01:33, 23 June 2015
Line 281:		Line 281:
	end architecture Behavioral;		end architecture Behavioral;
	</source>		</source>
		+
		+	[[Category:DMG]]

@@ Line 18: / Line 18: @@
 |5V supply
 |-
-|14
+|12
 |GND
 |PWR

@@ Line 78: / Line 78: @@
 |Low-Active ROM Chip Select
 |}
 {{clear|both}}

@@ Line 137: / Line 137: @@
 = Behavior =
-<syntaxhighlight lang="vhdl">
+<source lang="vhdl">
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ Line 278: / Line 278: @@
 end architecture Behavioral;
-</syntaxhighlight>
+</source>