MediaWiki API result
This is the HTML representation of the JSON format. HTML is good for debugging, but is unsuitable for application use.
Specify the format parameter to change the output format. To see the non-HTML representation of the JSON format, set format=json.
See the complete documentation, or the API help for more information.
{
"batchcomplete": "",
"continue": {
"gapcontinue": "Sachen_Mappers",
"continue": "gapcontinue||"
},
"query": {
"pages": {
"25": {
"pageid": 25,
"ns": 0,
"title": "Sachen MMC1",
"revisions": [
{
"contentformat": "text/x-wiki",
"contentmodel": "wikitext",
"*": "Sachen's MMC1 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.\n\n= Pinouts =\n\n<gallery widths=\"350px\" heights=\"400px\" style=\"text-align: center;\">\nImage:Sachen MMC1 Pinout.png\nImage:Sachen MMC1 Rom Pinout.png\n</gallery>\n\n{| class=\"wikitable pintable\" style=\"margin:1em auto; width: 66%;\"\n!style=\"width: 15%;\" | Pin No. MMC1\n!style=\"width: 15%;\" | Pin No. MMC1+ROM\n!style=\"width: 20%;\" | Name\n!style=\"width: 5%;\" | Type\n!style=\"width: 45%;\" | Comment\n|-\n|1, 36\n|1\n|VCC\n|PWR\n|5V supply\n|-\n|21, 35\n|17\n|GND\n|PWR\n|Ground supply\n|-\n|—\n|7–8, 26\n|GND?\n|PWR\n|Ground supply or unused pin.\n|-\n|18–20, 22–26\n|14–16, 18–22\n|D0–D7\n|I\n|Data Bus\n|-\n|—\n|25\n|{{Overline|RD}}\n|I\n|Low-Active Read Enable\n|-\n|29\n|32\n|{{Overline|WR}}\n|I\n|Low-Active Write Enable\n|-\n|8\n|2\n|{{Overline|RESET}}\n|I\n|Low-Active Asynchronous Reset\n|-\n|2–6, 32, 7, 28, 30, 9, 33–34, 27\n|13–9, 6–4, 29–28, 24, 27, 3, 30–31, 23\n|A0–A15\n|I\n|Address Bus\n|-\n|40–37\n|—\n|RA0, RA1, RA4, RA6\n|O\n|Scrambled lower ROM Address Lines\n|-\n|31\n|—\n|RA7\n|O\n|Lower ROM Address Lines\n|-\n|31, 17–10\n|—\n|RA14–RA21\n|O\n|Upper ROM Address Lines\n|-\n|—\n|—\n|NC\n|N/A\n|Not connected.\n|}\n\n= Theory of Operation =\n\nSachen's MMC1 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.\nTo avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.\n\n== Modes of Operation ==\n\nSachen MMC1 has two modes of operation ''locked'' and ''unlocked''. It defaults to ''locked'' after reset.\n\nThis is used to display the Sachen logo instead of the Nintendo logo for the DMG bootstrap ROM. While ''locked'', the mapper will keep RA7 set.\n\nThe unlock sequence is 0x31 transitions of A15 from high to low. Starting on the last transition, RA7 will follow A7. All control signals are don't cares for this.\n\nOther functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''\n\nThe only way to ''lock'' the mapper after ''unlocking'' is to reset it.\n\n== Header Scramble ==\n\nSachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:\n\n<pre>\nRA0 <= A6\nRA1 <= A4\nRA4 <= A1\nRA6 <= A0\n</pre>\n\nWhen A8 is low or A15..A9 are not low, RAn lines will track their respective An line.\n\n== Multi Memory Remap ==\n\nBase ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.\n\nThe mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre>\n\n= Memory Map =\n\n* <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0\n* <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank\n* <tt>0x8000-0xFFFF</tt>: Unmapped\n\nMapped here means adjusted for absolute Base ROM bank.\n\nThe RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.\n\n= Registers =\n\nWrite-Accessible Registers:\n\n* <tt>0x0000-0x1FFF</tt>: Base ROM bank register\n* <tt>0x2000-0x3FFF</tt>: ROM bank register\n* <tt>0x4000-0x5FFF</tt>: ROM bank mask register\n\n== ROM Bank Register ==\n\nThe ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.\n\n<pre>\nD7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset\n\\_____________________/\n \\___/ \\-------- ROM Bank\n |\n \\----------------- Map Enable\n</pre>\n\nROM Bank bits switch the bank mapped to 0x4000-0x7FFF.\nMap Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.\n\nThe width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.\n\n== Base ROM Bank Register ==\n\nThis register stores the base ROM bank.\n\n<pre>\nD7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset\n\\_____________________/\n \\-------- Base ROM Bank\n</pre>\n\nThis register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.\nChanges to this register take immediate effect.\n\n== ROM bank mask register ==\n\nThis register stores the ROM bank mask.\n\n<pre>\nD7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset\n\\_____________________/\n \\-------- ROM Bank Mask\n</pre>\n\nThis register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.\nChanges to this register take immediate effect.\n\n= Behavior =\n\n== Integrated ROM ==\n\nThe integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.\nDepending on the bonded ROM smaller ROMs may have an additional low-active CE line on RA17 or RA18.\n\n[[Category:DMG]]"
}
]
},
"26": {
"pageid": 26,
"ns": 0,
"title": "Sachen MMC2",
"revisions": [
{
"contentformat": "text/x-wiki",
"contentmodel": "wikitext",
"*": "Sachen's MMC2 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.\n\n= Pinouts =\n\n<gallery widths=\"350px\" heights=\"400px\" style=\"text-align: center;\">\nImage:Sachen MMC2 Pinout.png\nImage:Sachen MMC2 Rom PinoutA.png\nImage:Sachen MMC2 Rom PinoutB.png\n</gallery>\n\n{| class=\"wikitable pintable\" style=\"margin:1em auto; width: 66%;\"\n!style=\"width: 15%;\" | Pin No. MMC2\n!style=\"width: 15%;\" | Pin No. MMC2+ROM A (MMC2+ROM B)\n!style=\"width: 20%;\" | Name\n!style=\"width: 5%;\" | Type\n!style=\"width: 45%;\" | Comment\n|-\n|1\n|1, 36 (34)\n|VCC\n|PWR\n|5V supply\n|-\n|21, 38\n|32 (30)\n|GND\n|PWR\n|Ground supply\n|-\n|—\n|(30–31)\n|NC?\n|N/A\n|Unused pin.\n|-\n|6–5, 37–36, 27–26, 16–15\n|21–28\n|D0–D7\n|I\n|Data Bus\n|-\n|—\n|3\n|{{Overline|RD}}\n|I\n|Low-Active Read Enable\n|-\n|18\n|2\n|{{Overline|WR}}\n|I\n|Low-Active Write Enable\n|-\n|19\n|4\n|{{Overline|CS}}\n|I\n|Low-Active Chip Select\n|-\n|22\n|29\n|{{Overline|RESET}}\n|I\n|Low-Active Asynchronous Reset\n|-\n|35–32, 28, 25, 31–29, 24–23, 20, 17\n|5–20\n|A0–A15\n|I\n|Address Bus\n|-\n|4–2, 40\n|—\n|RA0, RA1, RA4, RA6\n|O\n|Scrambled lower ROM Address Lines\n|-\n|39\n|—\n|RA7\n|O\n|Lower ROM Address Lines\n|-\n|14–7\n|35 (33)\n|RA14–RA21 resp. RA19\n|O\n|Upper ROM Address Lines\n|-\n|—\n|34–33 (32–31)\n|OPT1–OPT2\n|I (PD)\n|Option Input Pins\n|-\n|—\n|—\n|NC\n|N/A\n|Not connected.\n|}\n\n= Theory of Operation =\n\nSachen's MMC2 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.\nTo avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.\n\nSachen added a detection method for Game Boy Color to successfully perform the logo switch, since the Game Boy Color changed the way the logo is checked.\n\n== Modes of Operation ==\n\nSachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.\n\nThis is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.\n\nWhile in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.\n\nThe unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.\nGoing from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.\nThe MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.\n\nOther functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.\n\nThe only way to ''lock'' the mapper after ''unlocking'' is to reset it.\n\n== Header Scramble ==\n\nSachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:\n\n<pre>\nRA0 <= A6\nRA1 <= A4\nRA4 <= A1\nRA6 <= A0\n</pre>\n\nWhen A8 is low or A15..A9 are not low, RAn lines will track their respective An line.\n\n== Multi Memory Remap ==\n\nBase ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.\n\nThe mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre>\n\n= Memory Map =\n\n* <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0\n* <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank\n* <tt>0x8000-0xFFFF</tt>: Unmapped\n\nMapped here means adjusted for absolute Base ROM bank.\n\nThe RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.\n\n= Registers =\n\nWrite-Accessible Registers:\n\n* <tt>0x0000-0x1FFF</tt>: Base ROM bank register\n* <tt>0x2000-0x3FFF</tt>: ROM bank register\n* <tt>0x4000-0x5FFF</tt>: ROM bank mask register\n\n== ROM Bank Register ==\n\nThe ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.\n\n<pre>\nD7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset\n\\_____________________/\n \\___/ \\-------- ROM Bank\n |\n \\----------------- Map Enable\n</pre>\n\nROM Bank bits switch the bank mapped to 0x4000-0x7FFF.\nMap Enable bits are used to enable write access to the [[#Base ROM Bank Register|#Base ROM Bank Register]] and [[#ROM bank mask register|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.\n\nThe width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.\n\n== Base ROM Bank Register ==\n\nThis register stores the base ROM bank.\n\n<pre>\nD7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset\n\\_____________________/\n \\-------- Base ROM Bank\n</pre>\n\nThis register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.\nChanges to this register take immediate effect.\n\n== ROM bank mask register ==\n\n\nThis register stores the ROM bank mask.\n\n<pre>\nD7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset\n\\_____________________/\n \\-------- ROM Bank Mask\n</pre>\n\nThis register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.\nChanges to this register take immediate effect.\n\n= Behavior =\n\n== Integrated ROM ==\n\nThe integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.\nROM chip enable behavior is: <pre>#ROM_CS = A15 or RA20 or OPT2</pre>\nThe highest address line (RA18) will behave as follows: <pre>RA18 = MMC1_RA18 or OPT1</pre>\n\n[[Category:DMG]]"
}
]
}
}
}
}