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https://wiki.tauwasser.eu/api.php?action=feedcontributions&feedformat=atom&user=Tauwasser Tauwasser's Wiki - User contributions [en] 2026-05-27T17:01:01Z User contributions MediaWiki 1.31.0 https://wiki.tauwasser.eu/index.php?title=Sachen_MMC1&diff=153 Sachen MMC1 2021-08-19T20:34:14Z

<p>Tauwasser: Categorize into DMG as this page is apparently hard to find.</p> <hr /> <div>Sachen's MMC1 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinouts =<br /> <br /> <gallery widths="350px" heights="400px" style="text-align: center;"><br /> Image:Sachen MMC1 Pinout.png<br /> Image:Sachen MMC1 Rom Pinout.png<br /> </gallery><br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 15%;" | Pin No. MMC1<br /> !style="width: 15%;" | Pin No. MMC1+ROM<br /> !style="width: 20%;" | Name<br /> !style="width: 5%;" | Type<br /> !style="width: 45%;" | Comment<br /> |-<br /> |1, 36<br /> |1<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |21, 35<br /> |17<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |&mdash;<br /> |7&ndash;8, 26<br /> |GND?<br /> |PWR<br /> |Ground supply or unused pin.<br /> |-<br /> |18&ndash;20, 22&ndash;26<br /> |14&ndash;16, 18&ndash;22<br /> |D0&ndash;D7<br /> |I<br /> |Data Bus<br /> |-<br /> |&mdash;<br /> |25<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |29<br /> |32<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |8<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |2&ndash;6, 32, 7, 28, 30, 9, 33&ndash;34, 27<br /> |13&ndash;9, 6&ndash;4, 29&ndash;28, 24, 27, 3, 30&ndash;31, 23<br /> |A0&ndash;A15<br /> |I<br /> |Address Bus<br /> |-<br /> |40&ndash;37<br /> |&mdash;<br /> |RA0, RA1, RA4, RA6<br /> |O<br /> |Scrambled lower ROM Address Lines<br /> |-<br /> |31<br /> |&mdash;<br /> |RA7<br /> |O<br /> |Lower ROM Address Lines<br /> |-<br /> |31, 17&ndash;10<br /> |&mdash;<br /> |RA14&ndash;RA21<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |&mdash;<br /> |&mdash;<br /> |NC<br /> |N/A<br /> |Not connected.<br /> |}<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC1 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC1 has two modes of operation ''locked'' and ''unlocked''. It defaults to ''locked'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG bootstrap ROM. While ''locked'', the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x31 transitions of A15 from high to low. Starting on the last transition, RA7 will follow A7. All control signals are don't cares for this.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =<br /> <br /> == Integrated ROM ==<br /> <br /> The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.<br /> Depending on the bonded ROM smaller ROMs may have an additional low-active CE line on RA17 or RA18.<br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC2&diff=152 Sachen MMC2 2021-08-19T20:33:53Z

<p>Tauwasser: Categorize into DMG as this page is apparently hard to find.</p> <hr /> <div>Sachen's MMC2 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinouts =<br /> <br /> <gallery widths="350px" heights="400px" style="text-align: center;"><br /> Image:Sachen MMC2 Pinout.png<br /> Image:Sachen MMC2 Rom PinoutA.png<br /> Image:Sachen MMC2 Rom PinoutB.png<br /> </gallery><br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 15%;" | Pin No. MMC2<br /> !style="width: 15%;" | Pin No. MMC2+ROM A (MMC2+ROM B)<br /> !style="width: 20%;" | Name<br /> !style="width: 5%;" | Type<br /> !style="width: 45%;" | Comment<br /> |-<br /> |1<br /> |1, 36 (34)<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |21, 38<br /> |32 (30)<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |&mdash;<br /> |(30&ndash;31)<br /> |NC?<br /> |N/A<br /> |Unused pin.<br /> |-<br /> |6&ndash;5, 37&ndash;36, 27&ndash;26, 16&ndash;15<br /> |21&ndash;28<br /> |D0&ndash;D7<br /> |I<br /> |Data Bus<br /> |-<br /> |&mdash;<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |18<br /> |2<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |19<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |22<br /> |29<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |35&ndash;32, 28, 25, 31&ndash;29, 24&ndash;23, 20, 17<br /> |5&ndash;20<br /> |A0&ndash;A15<br /> |I<br /> |Address Bus<br /> |-<br /> |4&ndash;2, 40<br /> |&mdash;<br /> |RA0, RA1, RA4, RA6<br /> |O<br /> |Scrambled lower ROM Address Lines<br /> |-<br /> |39<br /> |&mdash;<br /> |RA7<br /> |O<br /> |Lower ROM Address Lines<br /> |-<br /> |14&ndash;7<br /> |35 (33)<br /> |RA14&ndash;RA21 resp. RA19<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |&mdash;<br /> |34&ndash;33 (32&ndash;31)<br /> |OPT1&ndash;OPT2<br /> |I (PD)<br /> |Option Input Pins<br /> |-<br /> |&mdash;<br /> |&mdash;<br /> |NC<br /> |N/A<br /> |Not connected.<br /> |}<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC2 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> Sachen added a detection method for Game Boy Color to successfully perform the logo switch, since the Game Boy Color changed the way the logo is checked.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.<br /> <br /> While in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.<br /> Going from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.<br /> The MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register|#Base ROM Bank Register]] and [[#ROM bank mask register|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =<br /> <br /> == Integrated ROM ==<br /> <br /> The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.<br /> ROM chip enable behavior is: <pre>#ROM_CS = A15 or RA20 or OPT2</pre><br /> The highest address line (RA18) will behave as follows: <pre>RA18 = MMC1_RA18 or OPT1</pre><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01&diff=151 MMM01 2019-09-15T14:54:28Z

<p>Tauwasser: /* Separate MBC1 Mode #WE */ -- --> mdash</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MMM01 can be used to address up to 64&nbsp;Mbit of ROM and 1&nbsp;Mbit of SRAM depending on the mode MMM01 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MMM01 Pinout.png|center|x500px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;11<br /> |D6&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |1<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |13&ndash;15<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |16, 29, 27, 21&ndash;17, 22<br /> |RA22&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |26&ndash;23<br /> |AA16&ndash;AA13<br /> |O<br /> |Upper RAM Address Lines<br /> |-<br /> |32<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |-<br /> |31<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |30<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |}<br /> <br /> Footprint: QFP80P900X900-32<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. D6..D0, A15..A13, {{Overline|RD}}, {{Overline|WR}}, {{Overline|CS}} are internally pulled down with ~50&nbsp;kΩ<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \_________/<br /> | | \-------- RAM Enable<br /> | \----------------- Ram Bank #WE AA14..AA13<br /> \--------------------- Map Enable<br /> <br /> </pre><br /> <br /> * '''RAM Enable''': A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> * '''RAM Bank #WE''': Low-Active Write-Enable lines for the two least-significant RAM bank bits in [[#RAM Bank Register]]. Can only be written when '''Map Enable''' is reset.<br /> * '''Map Enable''': Setting this bit will disable write access to special register bits and disable the forced ROM Address line masking. Can only be written when '''Map Enable''' is reset.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \___/ \____________/<br /> | \-------- ROM Bank RA18..RA14<br /> \-------------------- ROM Bank RA20..RA19<br /> <br /> </pre><br /> <br /> * '''ROM Bank RA18..RA14''': These bits select the lower ROM address lines. The written value is zero-adjusted before output on RA18&ndash;RA14 based only on bits not masked by ROM Bank #WE/Mask RA18..RA15 in [[#Mode Register]].<br /> * '''ROM Bank RA20..RA19''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \___/ \___/<br /> | | | \----- RAM Bank AA14..AA13<br /> | | \----------- RAM Bank AA16..AA15<br /> | \----------------- ROM Bank RA22..RA21<br /> \--------------------- MBC1 Mode #WE<br /> <br /> </pre><br /> <br /> * '''RAM Bank AA14..AA13''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. The MBC1 mode settings still apply, see [[#Mode Register]].<br /> * '''RAM Bank AA16..AA15''': These bits select the upper RAM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''ROM Bank RA22..RA21''': These bits select the upper ROM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''MBC1 Mode #WE''': Low-Active Write Enable for MBC1 Mode in [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \_________/ | |<br /> | | | \--- MBC1 Mode<br /> | | \------ Unknown<br /> | \-------------- ROM Bank #WE/Mask RA18..RA15<br /> \--------------------- Multiplexer for AA14..AA13 and RA20..RA19<br /> <br /> </pre><br /> <br /> * '''MBC1 Mode''': Selects the MBC1 operating mode. 0 for 16&nbsp;Mbit/64&nbsp;kbit mode and 1 for 4&nbsp;MBit/256&nbsp;kbit. Can only be written when '''MBC1 Mode #WE''' in [[#RAM Bank Register]] is reset.<br /> * '''Unknown''': Setting or resetting this bit had no observable effect.<br /> * '''ROM Bank #WE/Mask RA18..RA15''': Low-Active Write-Enable for RA18..RA15 in [[#ROM Bank Register]] as well as mask for zero-adjusting RA18..RA15. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''Multiplexer''': The multiplexer will switch the bits output to pins AA14..AA13 and RA20..RA19. Barring MBC1 Mode logic: when reset, pins will be driven from register contents; when set, pins will be driven from the other register, i.e. RA20..RA19 will be driven by [[#RAM Bank Register]] and AA14..AA13 will be driven by [[#ROM Bank Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> = Operation =<br /> <br /> Operating the MMM01 can be quite complex and the register contents are not straightforward. This section will detail the programming model and give example configurations.<br /> <br /> == Modes of Operation ==<br /> <br /> Nintendo's MMM01 has two modes of operation ''mapped'' and ''unmapped''. It defaults to ''unmapped'' after reset.<br /> <br /> In ''unmapped'' state, the upper ROM address lines RA22..RA15 are all forced to 1, meaning the ROM entry point will be in ROM bank 0x1FE with the only other accessible ROM bank being 0x1FF.<br /> <br /> This is used to lock write access to the upper bits of the known [[MBC1]] registers after base ROM and RAM banks and masks have been set up.<br /> <br /> The only way to ''unmap'' the mapper after ''mapping'' is to reset it.<br /> <br /> == Programming Model ==<br /> <br /> All registers are live, e.g. Setting the RAM Bank #WE bits and subsequently writing to RAM Bank AA14..AA13 won't work -- no matter if in ''mapped'' of ''unmapped'' state. Therefore, there is a certain order in which registers are optimally written:<br /> <br /> # ROM Bank Register<br /> # Mode Register<br /> # RAM Register<br /> # RAM Enable<br /> <br /> Not all of Nintendo's games that use MMM01 keep with this order. However, due to the individual games' sizes and use of RAM banks, this isn't noticeable when the games don't misbehave.<br /> <br /> Most Rom Address line changes cannot be observed in ''unmapped'' mode due to the mapper starting at ROM bank 0x1FE and 0x1FF (depending on A14) until ''mapped''.<br /> <br /> == Map MBC1 Mode 0: 16&nbsp;Mbit/64&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "0", Mux = "1"<br /> <br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (common) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (uncommon) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "1"<br /> <br /> This is probably not the intended use case.<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/256&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> = Remarks =<br /> <br /> == Unknown Bit ==<br /> <br /> There is an Unknown bit in [[#Mode Register]] whose use -- if any -- could not be determined through testing. It is definitely not ROM Bank RA14 #WE as RA14 can be written at all times -- hence there cannot be a single bank mapped to both regions. It might be part of ROM Bank RA14 Mask and an Engineer might have missed that the zero-adjustment logic means that this bit is not necessary.<br /> <br /> == SRAM Enable/Disable ==<br /> <br /> The most glaringly missing feature of MMM01 is an option to disable SRAM access for individual games. The Unknown bit in [[#Mode Register]] does not provide for this either. The only commercial cartridge containing MMM01 and SRAM is Momotarou Collection 2 and it tries to sacrifice one SRAM bank to make sure that one game has no chance of deleting the other's save file. However, the PCB only has one 64 KiB SRAM and the RAM address lines are all unconnected.<br /> <br /> Having to spend 64&nbsp;kBit to ''disable'' SRAM access seems like a waste considering a simple OR-gate could have stopped SRAM access.<br /> <br /> == Separate MBC1 Mode #WE ==<br /> <br /> The MBC1 Mode #WE stands out as being separated from mapping logic. Instead, if its #WE is not deasserted, it can be freely written even in mapped mode. However, the address line multiplexing for 16&nbsp;Mbit and 4&nbsp;Mbit does not switch with the mode setting&mdash;which given a fixed ROM/SRAM wiring on the cartridge&mdash;would need to be done in order for a hypothetical 16&nbsp;Mbit/256&nbsp;kBit mode to be feasible.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MMM01 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(6 downto 0);<br /> RA : out std_logic_vector(22 downto 14);<br /> AA : out std_logic_vector(16 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MMM01;<br /> <br /> architecture Behavioral of MMM01 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal ram_bank_we_n_r : std_logic_vector(1 downto 0);<br /> signal latch_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_r : std_logic_vector(8 downto 0);<br /> signal ram_bank_r : std_logic_vector(3 downto 0);<br /> signal mode_we_n_r : std_logic_vector(6 downto 6);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_we_n_r : std_logic_vector(4 downto 1);<br /> signal mux_r : std_logic_vector(0 downto 0);<br /> <br /> signal ra_int : std_logic_vector(4 downto 0);<br /> signal aa_int : std_logic_vector(1 downto 0);<br /> <br /> signal ra_lo : std_logic_vector(4 downto 0);<br /> signal ra_mask : std_logic_vector(4 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> alias rom_bank_r_lo : std_logic_vector(4 downto 0) is rom_bank_r(4 downto 0);<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when (A(15) = '0' and RD_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> ra_lo <= "11110" when (latch_r = "0") else<br /> rom_bank_r_lo;<br /> <br /> ra_mask <= "11110" when (latch_r = "0") else<br /> rom_bank_we_n_r & "0";<br /> <br /> ra_int <= "00000" when (A(14) = '0') else<br /> ra_lo when ((ra_lo and not(ra_mask)) /= "00000") else<br /> "00001";<br /> <br /> aa_int <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r(1 downto 0);<br /> <br /> AA(16 downto 15) <= ram_bank_r(3 downto 2);<br /> AA(14 downto 13) <= aa_int when (mux_r = "0") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(22 downto 21) <= "11" when (latch_r = "0") else<br /> rom_bank_r(8 downto 7);<br /> <br /> RA(20 downto 19) <= "11" when (latch_r = "0") else<br /> aa_int when (mux_r = "1") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(18 downto 14) <= (ra_lo and ra_mask) or (ra_int and not(ra_mask));<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> ram_bank_we_n_r <= "00";<br /> latch_r <= "0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> if (latch_r = "0") then<br /> ram_bank_we_n_r <= D(5 downto 4);<br /> latch_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r(6 downto 0) <= "0000000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r(0) <= D(0);<br /> <br /> for i in rom_bank_we_n_r'range loop<br /> if (rom_bank_we_n_r(i) = '0') then<br /> rom_bank_r_lo(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> rom_bank_r(6 downto 5) <= D(6 downto 5);<br /> end if;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "0000";<br /> rom_bank_r(8 downto 7) <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> for i in ram_bank_we_n_r'range loop<br /> if (ram_bank_we_n_r(i) = '0') then<br /> ram_bank_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> ram_bank_r(3 downto 2) <= D(3 downto 2);<br /> rom_bank_r(8 downto 7) <= D(5 downto 4);<br /> mode_we_n_r <= D(6 downto 6);<br /> end if;<br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> rom_bank_we_n_r <= "0000";<br /> mux_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> for i in mode_we_n_r'range loop<br /> if (mode_we_n_r(i) = '0') then<br /> mode_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "1") then<br /> rom_bank_we_n_r <= D(5 downto 2);<br /> mux_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01&diff=150 MMM01 2019-09-15T14:53:22Z

<p>Tauwasser: /* SRAM Enable/Disable */ sp</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MMM01 can be used to address up to 64&nbsp;Mbit of ROM and 1&nbsp;Mbit of SRAM depending on the mode MMM01 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MMM01 Pinout.png|center|x500px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;11<br /> |D6&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |1<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |13&ndash;15<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |16, 29, 27, 21&ndash;17, 22<br /> |RA22&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |26&ndash;23<br /> |AA16&ndash;AA13<br /> |O<br /> |Upper RAM Address Lines<br /> |-<br /> |32<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |-<br /> |31<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |30<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |}<br /> <br /> Footprint: QFP80P900X900-32<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. D6..D0, A15..A13, {{Overline|RD}}, {{Overline|WR}}, {{Overline|CS}} are internally pulled down with ~50&nbsp;kΩ<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \_________/<br /> | | \-------- RAM Enable<br /> | \----------------- Ram Bank #WE AA14..AA13<br /> \--------------------- Map Enable<br /> <br /> </pre><br /> <br /> * '''RAM Enable''': A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> * '''RAM Bank #WE''': Low-Active Write-Enable lines for the two least-significant RAM bank bits in [[#RAM Bank Register]]. Can only be written when '''Map Enable''' is reset.<br /> * '''Map Enable''': Setting this bit will disable write access to special register bits and disable the forced ROM Address line masking. Can only be written when '''Map Enable''' is reset.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \___/ \____________/<br /> | \-------- ROM Bank RA18..RA14<br /> \-------------------- ROM Bank RA20..RA19<br /> <br /> </pre><br /> <br /> * '''ROM Bank RA18..RA14''': These bits select the lower ROM address lines. The written value is zero-adjusted before output on RA18&ndash;RA14 based only on bits not masked by ROM Bank #WE/Mask RA18..RA15 in [[#Mode Register]].<br /> * '''ROM Bank RA20..RA19''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \___/ \___/<br /> | | | \----- RAM Bank AA14..AA13<br /> | | \----------- RAM Bank AA16..AA15<br /> | \----------------- ROM Bank RA22..RA21<br /> \--------------------- MBC1 Mode #WE<br /> <br /> </pre><br /> <br /> * '''RAM Bank AA14..AA13''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. The MBC1 mode settings still apply, see [[#Mode Register]].<br /> * '''RAM Bank AA16..AA15''': These bits select the upper RAM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''ROM Bank RA22..RA21''': These bits select the upper ROM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''MBC1 Mode #WE''': Low-Active Write Enable for MBC1 Mode in [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \_________/ | |<br /> | | | \--- MBC1 Mode<br /> | | \------ Unknown<br /> | \-------------- ROM Bank #WE/Mask RA18..RA15<br /> \--------------------- Multiplexer for AA14..AA13 and RA20..RA19<br /> <br /> </pre><br /> <br /> * '''MBC1 Mode''': Selects the MBC1 operating mode. 0 for 16&nbsp;Mbit/64&nbsp;kbit mode and 1 for 4&nbsp;MBit/256&nbsp;kbit. Can only be written when '''MBC1 Mode #WE''' in [[#RAM Bank Register]] is reset.<br /> * '''Unknown''': Setting or resetting this bit had no observable effect.<br /> * '''ROM Bank #WE/Mask RA18..RA15''': Low-Active Write-Enable for RA18..RA15 in [[#ROM Bank Register]] as well as mask for zero-adjusting RA18..RA15. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''Multiplexer''': The multiplexer will switch the bits output to pins AA14..AA13 and RA20..RA19. Barring MBC1 Mode logic: when reset, pins will be driven from register contents; when set, pins will be driven from the other register, i.e. RA20..RA19 will be driven by [[#RAM Bank Register]] and AA14..AA13 will be driven by [[#ROM Bank Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> = Operation =<br /> <br /> Operating the MMM01 can be quite complex and the register contents are not straightforward. This section will detail the programming model and give example configurations.<br /> <br /> == Modes of Operation ==<br /> <br /> Nintendo's MMM01 has two modes of operation ''mapped'' and ''unmapped''. It defaults to ''unmapped'' after reset.<br /> <br /> In ''unmapped'' state, the upper ROM address lines RA22..RA15 are all forced to 1, meaning the ROM entry point will be in ROM bank 0x1FE with the only other accessible ROM bank being 0x1FF.<br /> <br /> This is used to lock write access to the upper bits of the known [[MBC1]] registers after base ROM and RAM banks and masks have been set up.<br /> <br /> The only way to ''unmap'' the mapper after ''mapping'' is to reset it.<br /> <br /> == Programming Model ==<br /> <br /> All registers are live, e.g. Setting the RAM Bank #WE bits and subsequently writing to RAM Bank AA14..AA13 won't work -- no matter if in ''mapped'' of ''unmapped'' state. Therefore, there is a certain order in which registers are optimally written:<br /> <br /> # ROM Bank Register<br /> # Mode Register<br /> # RAM Register<br /> # RAM Enable<br /> <br /> Not all of Nintendo's games that use MMM01 keep with this order. However, due to the individual games' sizes and use of RAM banks, this isn't noticeable when the games don't misbehave.<br /> <br /> Most Rom Address line changes cannot be observed in ''unmapped'' mode due to the mapper starting at ROM bank 0x1FE and 0x1FF (depending on A14) until ''mapped''.<br /> <br /> == Map MBC1 Mode 0: 16&nbsp;Mbit/64&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "0", Mux = "1"<br /> <br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (common) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (uncommon) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "1"<br /> <br /> This is probably not the intended use case.<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/256&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> = Remarks =<br /> <br /> == Unknown Bit ==<br /> <br /> There is an Unknown bit in [[#Mode Register]] whose use -- if any -- could not be determined through testing. It is definitely not ROM Bank RA14 #WE as RA14 can be written at all times -- hence there cannot be a single bank mapped to both regions. It might be part of ROM Bank RA14 Mask and an Engineer might have missed that the zero-adjustment logic means that this bit is not necessary.<br /> <br /> == SRAM Enable/Disable ==<br /> <br /> The most glaringly missing feature of MMM01 is an option to disable SRAM access for individual games. The Unknown bit in [[#Mode Register]] does not provide for this either. The only commercial cartridge containing MMM01 and SRAM is Momotarou Collection 2 and it tries to sacrifice one SRAM bank to make sure that one game has no chance of deleting the other's save file. However, the PCB only has one 64 KiB SRAM and the RAM address lines are all unconnected.<br /> <br /> Having to spend 64&nbsp;kBit to ''disable'' SRAM access seems like a waste considering a simple OR-gate could have stopped SRAM access.<br /> <br /> == Separate MBC1 Mode #WE ==<br /> <br /> The MBC1 Mode #WE stands out as being separated from mapping logic. Instead, if its #WE is not deasserted, it can be freely written even in mapped mode. However, the address line multiplexing for 16&nbsp;Mbit and 4&nbsp;Mbit does not switch with the mode setting -- which given a fixed ROM/SRAM wiring on the cartridge -- would need to be done in order for a hypothetical 16&nbsp;Mbit/256&nbsp;kBit mode to be feasible.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MMM01 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(6 downto 0);<br /> RA : out std_logic_vector(22 downto 14);<br /> AA : out std_logic_vector(16 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MMM01;<br /> <br /> architecture Behavioral of MMM01 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal ram_bank_we_n_r : std_logic_vector(1 downto 0);<br /> signal latch_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_r : std_logic_vector(8 downto 0);<br /> signal ram_bank_r : std_logic_vector(3 downto 0);<br /> signal mode_we_n_r : std_logic_vector(6 downto 6);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_we_n_r : std_logic_vector(4 downto 1);<br /> signal mux_r : std_logic_vector(0 downto 0);<br /> <br /> signal ra_int : std_logic_vector(4 downto 0);<br /> signal aa_int : std_logic_vector(1 downto 0);<br /> <br /> signal ra_lo : std_logic_vector(4 downto 0);<br /> signal ra_mask : std_logic_vector(4 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> alias rom_bank_r_lo : std_logic_vector(4 downto 0) is rom_bank_r(4 downto 0);<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when (A(15) = '0' and RD_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> ra_lo <= "11110" when (latch_r = "0") else<br /> rom_bank_r_lo;<br /> <br /> ra_mask <= "11110" when (latch_r = "0") else<br /> rom_bank_we_n_r & "0";<br /> <br /> ra_int <= "00000" when (A(14) = '0') else<br /> ra_lo when ((ra_lo and not(ra_mask)) /= "00000") else<br /> "00001";<br /> <br /> aa_int <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r(1 downto 0);<br /> <br /> AA(16 downto 15) <= ram_bank_r(3 downto 2);<br /> AA(14 downto 13) <= aa_int when (mux_r = "0") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(22 downto 21) <= "11" when (latch_r = "0") else<br /> rom_bank_r(8 downto 7);<br /> <br /> RA(20 downto 19) <= "11" when (latch_r = "0") else<br /> aa_int when (mux_r = "1") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(18 downto 14) <= (ra_lo and ra_mask) or (ra_int and not(ra_mask));<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> ram_bank_we_n_r <= "00";<br /> latch_r <= "0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> if (latch_r = "0") then<br /> ram_bank_we_n_r <= D(5 downto 4);<br /> latch_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r(6 downto 0) <= "0000000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r(0) <= D(0);<br /> <br /> for i in rom_bank_we_n_r'range loop<br /> if (rom_bank_we_n_r(i) = '0') then<br /> rom_bank_r_lo(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> rom_bank_r(6 downto 5) <= D(6 downto 5);<br /> end if;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "0000";<br /> rom_bank_r(8 downto 7) <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> for i in ram_bank_we_n_r'range loop<br /> if (ram_bank_we_n_r(i) = '0') then<br /> ram_bank_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> ram_bank_r(3 downto 2) <= D(3 downto 2);<br /> rom_bank_r(8 downto 7) <= D(5 downto 4);<br /> mode_we_n_r <= D(6 downto 6);<br /> end if;<br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> rom_bank_we_n_r <= "0000";<br /> mux_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> for i in mode_we_n_r'range loop<br /> if (mode_we_n_r(i) = '0') then<br /> mode_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "1") then<br /> rom_bank_we_n_r <= D(5 downto 2);<br /> mux_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01_Games&diff=149 MMM01 Games 2019-05-01T19:54:14Z

<p>Tauwasser: /* Settings */ spell out settings and mistake in code</p> <hr /> <div>__TOC__<br /> <br /> This page lists games that use Nintendo's [[MMM01]], their ROM layout and the configuration settings they use per game.<br /> <br /> = Momotarou Collection 2 =<br /> <br /> ROM: '''Momotarou Collection 2 (Japan)''' (2B589E58D8821C59B7AF702723361DB5)<br /> <br /> PCB: '''DMG-MC-SFCN-01'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Momotarou Dengeki 2<br /> |0x00&ndash;0x1F<br /> |-<br /> |0x20<br /> |Momotarou Gaiden<br /> |0x20&ndash;0x2F<br /> |-<br /> |0x3E<br /> |Menu<br /> |0x3E&ndash;0x3F<br /> |}<br /> <br /> ROM banks 0x30&ndash;0x3D are unused and filled with 0xFF.<br /> <br /> == Settings ==<br /> <br /> Code at 3E:3A0F resp. 3E:3A2C depending on the game.<br /> <br /> === Momotarou Gaiden ===<br /> <br /> 3FFF <= 20 -01 00000<br /> 5FFF <= 40 -1 0000 00<br /> 7FFF <= 21 -0 1000 01<br /> 1FFF <= 3A -0 11 1010<br /> 1FFF <= 7A -1 11 1010<br /> <br /> Resulting configuration:<br /> <br /> R0: SRAM Enable | AA Mask 0x03<br /> R1: RA 0x20<br /> R2: AA 0x00 | MBC1 Mode #WE deasserted<br /> R3: RA Mask 0x20 | MBC1 Mode 16 MBit/64 kBit (*)<br /> <br /> (*) Code disables access to MBC1 Mode register before writing it. Therefore setting MBC1 Mode to 4 MBit/256 kBit fails here.<br /> <br /> === Momotarou Dengeki 2 ===<br /> <br /> 3FFF <= 00 -00 00000<br /> 5FFF <= 01 -0 0000 01<br /> 7FFF <= 01 -0 0000 01<br /> 1FFF <= 3A -0 11 1010<br /> 1FFF <= 7A -1 11 1010<br /> <br /> Resulting configuration:<br /> <br /> R0: SRAM Enable | AA Mask 0x03<br /> R1: RA 0x00<br /> R2: AA 0x01 | MBC1 Mode #WE asserted<br /> R3: MBC1 Mode 4 MBit/256 kBit<br /> <br /> = Taito Variety Pack =<br /> <br /> ROM: '''Taito Variety Pack (Japan)''' (FC84B2E016917D5B0E7DE412D9F8C269)<br /> <br /> PCB: '''DMG-M-PEAN-10'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Sagaia<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Chase H.Q.<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bubble Bobble<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Elevator Action<br /> |0x18&ndash;0x1B<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x1C&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Bubble Bobble ===<br /> <br /> 2000 <= 70 -11 10000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Elevator Action ===<br /> <br /> 2000 <= 78 -11 11000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Chase H.Q. ===<br /> <br /> 2000 <= 68 -11 01000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Sagaia ===<br /> <br /> 2000 <= 60 -11 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Taito) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-602)''' (D57F73C47ACA3E22F4EA2143469AB20E)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> This is the [[#Taito Variety Pack]] released by Mani in China with a different menu.<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Sagaia<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Chase H.Q.<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bubble Bobble<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Elevator Action<br /> |0x18&ndash;0x1B<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x1C&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Bubble Bobble ===<br /> <br /> 2000 <= 70 -11 10000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Elevator Action ===<br /> <br /> 2000 <= 78 -11 11000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Chase H.Q. ===<br /> <br /> 2000 <= 68 -11 01000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Sagaia ===<br /> <br /> 2000 <= 60 -11 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Tomy) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-603)''' (D9293475642991E942AC11262D8E5927)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Ganbaruga<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Esparks<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Raijinou<br /> |0x10&ndash;0x13<br /> |-<br /> |0x14<br /> |Zoids<br /> |0x14&ndash;0x17<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x18&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Ganbaruga ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Raijinou ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Zoids ===<br /> <br /> 2000 <= 14 -00 10100<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Esparks ===<br /> <br /> 2000 <= 08 -00 01000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (irem) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-604)''' (203FD4178EE332D1B2CF24504716C885)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |R-Type 2<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Ninja Spirit<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Ganso!! Yancha-Maru<br /> |0x10&ndash;0x13<br /> |-<br /> |0x14<br /> |Match-Mania<br /> |0x14&ndash;0x15<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x16&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === R-Type 2 ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Ninja Spirit ===<br /> <br /> 2000 <= 08 -00 01000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Ganso!! Yancha-Maru ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Match-Mania ===<br /> <br /> 2000 <= 14 -00 10100<br /> 6000 <= 3C -0 1111 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Hudson) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-605)''' (3EB5EBDA098635B2DA0021F46A959DE4)<br /> <br /> PCB: '''DMG-MMM-BEAN-M13'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |GB Genjin<br /> |0x00&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bomber Boy<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Milon Castle<br /> |0x18&ndash;0x1F<br /> |-<br /> |0x20<br /> |Boukenjima 2<br /> |0x20&ndash;0x27<br /> |-<br /> |0x3E<br /> |Menu<br /> |0x3E&ndash;0x3F<br /> |}<br /> ROM banks 0x28&ndash;0x3D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Boukenjima 2 ===<br /> <br /> 2000 <= 20 -01 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === GB Genjin ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 20 -0 1000 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Bomber Boy ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Milon Castle ===<br /> <br /> 2000 <= 18 -00 11000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01&diff=148 MMM01 2019-05-01T19:28:45Z

<p>Tauwasser: /* SRAM Enable/Disable */ clarify</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MMM01 can be used to address up to 64&nbsp;Mbit of ROM and 1&nbsp;Mbit of SRAM depending on the mode MMM01 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MMM01 Pinout.png|center|x500px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;11<br /> |D6&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |1<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |13&ndash;15<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |16, 29, 27, 21&ndash;17, 22<br /> |RA22&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |26&ndash;23<br /> |AA16&ndash;AA13<br /> |O<br /> |Upper RAM Address Lines<br /> |-<br /> |32<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |-<br /> |31<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |30<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |}<br /> <br /> Footprint: QFP80P900X900-32<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. D6..D0, A15..A13, {{Overline|RD}}, {{Overline|WR}}, {{Overline|CS}} are internally pulled down with ~50&nbsp;kΩ<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \_________/<br /> | | \-------- RAM Enable<br /> | \----------------- Ram Bank #WE AA14..AA13<br /> \--------------------- Map Enable<br /> <br /> </pre><br /> <br /> * '''RAM Enable''': A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> * '''RAM Bank #WE''': Low-Active Write-Enable lines for the two least-significant RAM bank bits in [[#RAM Bank Register]]. Can only be written when '''Map Enable''' is reset.<br /> * '''Map Enable''': Setting this bit will disable write access to special register bits and disable the forced ROM Address line masking. Can only be written when '''Map Enable''' is reset.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \___/ \____________/<br /> | \-------- ROM Bank RA18..RA14<br /> \-------------------- ROM Bank RA20..RA19<br /> <br /> </pre><br /> <br /> * '''ROM Bank RA18..RA14''': These bits select the lower ROM address lines. The written value is zero-adjusted before output on RA18&ndash;RA14 based only on bits not masked by ROM Bank #WE/Mask RA18..RA15 in [[#Mode Register]].<br /> * '''ROM Bank RA20..RA19''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \___/ \___/<br /> | | | \----- RAM Bank AA14..AA13<br /> | | \----------- RAM Bank AA16..AA15<br /> | \----------------- ROM Bank RA22..RA21<br /> \--------------------- MBC1 Mode #WE<br /> <br /> </pre><br /> <br /> * '''RAM Bank AA14..AA13''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. The MBC1 mode settings still apply, see [[#Mode Register]].<br /> * '''RAM Bank AA16..AA15''': These bits select the upper RAM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''ROM Bank RA22..RA21''': These bits select the upper ROM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''MBC1 Mode #WE''': Low-Active Write Enable for MBC1 Mode in [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \_________/ | |<br /> | | | \--- MBC1 Mode<br /> | | \------ Unknown<br /> | \-------------- ROM Bank #WE/Mask RA18..RA15<br /> \--------------------- Multiplexer for AA14..AA13 and RA20..RA19<br /> <br /> </pre><br /> <br /> * '''MBC1 Mode''': Selects the MBC1 operating mode. 0 for 16&nbsp;Mbit/64&nbsp;kbit mode and 1 for 4&nbsp;MBit/256&nbsp;kbit. Can only be written when '''MBC1 Mode #WE''' in [[#RAM Bank Register]] is reset.<br /> * '''Unknown''': Setting or resetting this bit had no observable effect.<br /> * '''ROM Bank #WE/Mask RA18..RA15''': Low-Active Write-Enable for RA18..RA15 in [[#ROM Bank Register]] as well as mask for zero-adjusting RA18..RA15. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''Multiplexer''': The multiplexer will switch the bits output to pins AA14..AA13 and RA20..RA19. Barring MBC1 Mode logic: when reset, pins will be driven from register contents; when set, pins will be driven from the other register, i.e. RA20..RA19 will be driven by [[#RAM Bank Register]] and AA14..AA13 will be driven by [[#ROM Bank Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> = Operation =<br /> <br /> Operating the MMM01 can be quite complex and the register contents are not straightforward. This section will detail the programming model and give example configurations.<br /> <br /> == Modes of Operation ==<br /> <br /> Nintendo's MMM01 has two modes of operation ''mapped'' and ''unmapped''. It defaults to ''unmapped'' after reset.<br /> <br /> In ''unmapped'' state, the upper ROM address lines RA22..RA15 are all forced to 1, meaning the ROM entry point will be in ROM bank 0x1FE with the only other accessible ROM bank being 0x1FF.<br /> <br /> This is used to lock write access to the upper bits of the known [[MBC1]] registers after base ROM and RAM banks and masks have been set up.<br /> <br /> The only way to ''unmap'' the mapper after ''mapping'' is to reset it.<br /> <br /> == Programming Model ==<br /> <br /> All registers are live, e.g. Setting the RAM Bank #WE bits and subsequently writing to RAM Bank AA14..AA13 won't work -- no matter if in ''mapped'' of ''unmapped'' state. Therefore, there is a certain order in which registers are optimally written:<br /> <br /> # ROM Bank Register<br /> # Mode Register<br /> # RAM Register<br /> # RAM Enable<br /> <br /> Not all of Nintendo's games that use MMM01 keep with this order. However, due to the individual games' sizes and use of RAM banks, this isn't noticeable when the games don't misbehave.<br /> <br /> Most Rom Address line changes cannot be observed in ''unmapped'' mode due to the mapper starting at ROM bank 0x1FE and 0x1FF (depending on A14) until ''mapped''.<br /> <br /> == Map MBC1 Mode 0: 16&nbsp;Mbit/64&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "0", Mux = "1"<br /> <br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (common) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (uncommon) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "1"<br /> <br /> This is probably not the intended use case.<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/256&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> = Remarks =<br /> <br /> == Unknown Bit ==<br /> <br /> There is an Unknown bit in [[#Mode Register]] whose use -- if any -- could not be determined through testing. It is definitely not ROM Bank RA14 #WE as RA14 can be written at all times -- hence there cannot be a single bank mapped to both regions. It might be part of ROM Bank RA14 Mask and an Engineer might have missed that the zero-adjustment logic means that this bit is not necessary.<br /> <br /> == SRAM Enable/Disable ==<br /> <br /> The most glaringly missing feature of MMM01 is an option to disable SRAM access for individual games. The Unknown bit in [[#Mode Register]] does not provide for this either. The only commercial cartridge containing MMM01 and SRAM is Momotarou Collection 2 and it tries to sacrifices one SRAM bank to make sure that one game has no chance of deleting the other's save file. However, the PCB only has one 64 KiB SRAM and the RAM address lines are all unconnected.<br /> <br /> Having to spend 64&nbsp;kBit to ''disable'' SRAM access seems like a waste considering a simple OR-gate could have stopped SRAM access.<br /> <br /> == Separate MBC1 Mode #WE ==<br /> <br /> The MBC1 Mode #WE stands out as being separated from mapping logic. Instead, if its #WE is not deasserted, it can be freely written even in mapped mode. However, the address line multiplexing for 16&nbsp;Mbit and 4&nbsp;Mbit does not switch with the mode setting -- which given a fixed ROM/SRAM wiring on the cartridge -- would need to be done in order for a hypothetical 16&nbsp;Mbit/256&nbsp;kBit mode to be feasible.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MMM01 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(6 downto 0);<br /> RA : out std_logic_vector(22 downto 14);<br /> AA : out std_logic_vector(16 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MMM01;<br /> <br /> architecture Behavioral of MMM01 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal ram_bank_we_n_r : std_logic_vector(1 downto 0);<br /> signal latch_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_r : std_logic_vector(8 downto 0);<br /> signal ram_bank_r : std_logic_vector(3 downto 0);<br /> signal mode_we_n_r : std_logic_vector(6 downto 6);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_we_n_r : std_logic_vector(4 downto 1);<br /> signal mux_r : std_logic_vector(0 downto 0);<br /> <br /> signal ra_int : std_logic_vector(4 downto 0);<br /> signal aa_int : std_logic_vector(1 downto 0);<br /> <br /> signal ra_lo : std_logic_vector(4 downto 0);<br /> signal ra_mask : std_logic_vector(4 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> alias rom_bank_r_lo : std_logic_vector(4 downto 0) is rom_bank_r(4 downto 0);<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when (A(15) = '0' and RD_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> ra_lo <= "11110" when (latch_r = "0") else<br /> rom_bank_r_lo;<br /> <br /> ra_mask <= "11110" when (latch_r = "0") else<br /> rom_bank_we_n_r & "0";<br /> <br /> ra_int <= "00000" when (A(14) = '0') else<br /> ra_lo when ((ra_lo and not(ra_mask)) /= "00000") else<br /> "00001";<br /> <br /> aa_int <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r(1 downto 0);<br /> <br /> AA(16 downto 15) <= ram_bank_r(3 downto 2);<br /> AA(14 downto 13) <= aa_int when (mux_r = "0") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(22 downto 21) <= "11" when (latch_r = "0") else<br /> rom_bank_r(8 downto 7);<br /> <br /> RA(20 downto 19) <= "11" when (latch_r = "0") else<br /> aa_int when (mux_r = "1") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(18 downto 14) <= (ra_lo and ra_mask) or (ra_int and not(ra_mask));<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> ram_bank_we_n_r <= "00";<br /> latch_r <= "0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> if (latch_r = "0") then<br /> ram_bank_we_n_r <= D(5 downto 4);<br /> latch_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r(6 downto 0) <= "0000000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r(0) <= D(0);<br /> <br /> for i in rom_bank_we_n_r'range loop<br /> if (rom_bank_we_n_r(i) = '0') then<br /> rom_bank_r_lo(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> rom_bank_r(6 downto 5) <= D(6 downto 5);<br /> end if;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "0000";<br /> rom_bank_r(8 downto 7) <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> for i in ram_bank_we_n_r'range loop<br /> if (ram_bank_we_n_r(i) = '0') then<br /> ram_bank_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> ram_bank_r(3 downto 2) <= D(3 downto 2);<br /> rom_bank_r(8 downto 7) <= D(5 downto 4);<br /> mode_we_n_r <= D(6 downto 6);<br /> end if;<br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> rom_bank_we_n_r <= "0000";<br /> mux_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> for i in mode_we_n_r'range loop<br /> if (mode_we_n_r(i) = '0') then<br /> mode_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "1") then<br /> rom_bank_we_n_r <= D(5 downto 2);<br /> mux_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01_Games&diff=147 MMM01 Games 2019-05-01T17:40:52Z

<p>Tauwasser: /* Momotarou Dengeki 2 */ fix register writes for dengeki 2</p> <hr /> <div>__TOC__<br /> <br /> This page lists games that use Nintendo's [[MMM01]], their ROM layout and the configuration settings they use per game.<br /> <br /> = Momotarou Collection 2 =<br /> <br /> ROM: '''Momotarou Collection 2 (Japan)''' (2B589E58D8821C59B7AF702723361DB5)<br /> <br /> PCB: '''DMG-MC-SFCN-01'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Momotarou Dengeki 2<br /> |0x00&ndash;0x1F<br /> |-<br /> |0x20<br /> |Momotarou Gaiden<br /> |0x20&ndash;0x2F<br /> |-<br /> |0x3E<br /> |Menu<br /> |0x3E&ndash;0x3F<br /> |}<br /> <br /> ROM banks 0x30&ndash;0x3D are unused and filled with 0xFF.<br /> <br /> == Settings ==<br /> <br /> === Momotarou Gaiden ===<br /> <br /> 3FFF <= 20 -01 00000<br /> 5FFF <= 40 -1 0000 00<br /> 7FFF <= 21 -0 1000 01<br /> 1FFF <= 3A -0 11 1010<br /> 1FFF <= 7A -1 11 1010<br /> <br /> === Momotarou Dengeki 2 ===<br /> <br /> 3FFF <= 00 -00 00000<br /> 5FFF <= 01 -0 0000 01<br /> 7FFF <= 01 -0 0000 01<br /> 1FFF <= 3A -0 11 1010<br /> 1FFF <= 7A -1 11 1010<br /> <br /> = Taito Variety Pack =<br /> <br /> ROM: '''Taito Variety Pack (Japan)''' (FC84B2E016917D5B0E7DE412D9F8C269)<br /> <br /> PCB: '''DMG-M-PEAN-10'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Sagaia<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Chase H.Q.<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bubble Bobble<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Elevator Action<br /> |0x18&ndash;0x1B<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x1C&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Bubble Bobble ===<br /> <br /> 2000 <= 70 -11 10000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Elevator Action ===<br /> <br /> 2000 <= 78 -11 11000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Chase H.Q. ===<br /> <br /> 2000 <= 68 -11 01000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Sagaia ===<br /> <br /> 2000 <= 60 -11 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Taito) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-602)''' (D57F73C47ACA3E22F4EA2143469AB20E)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> This is the [[#Taito Variety Pack]] released by Mani in China with a different menu.<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Sagaia<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Chase H.Q.<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bubble Bobble<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Elevator Action<br /> |0x18&ndash;0x1B<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x1C&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Bubble Bobble ===<br /> <br /> 2000 <= 70 -11 10000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Elevator Action ===<br /> <br /> 2000 <= 78 -11 11000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Chase H.Q. ===<br /> <br /> 2000 <= 68 -11 01000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Sagaia ===<br /> <br /> 2000 <= 60 -11 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Tomy) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-603)''' (D9293475642991E942AC11262D8E5927)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Ganbaruga<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Esparks<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Raijinou<br /> |0x10&ndash;0x13<br /> |-<br /> |0x14<br /> |Zoids<br /> |0x14&ndash;0x17<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x18&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Ganbaruga ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Raijinou ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Zoids ===<br /> <br /> 2000 <= 14 -00 10100<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Esparks ===<br /> <br /> 2000 <= 08 -00 01000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (irem) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-604)''' (203FD4178EE332D1B2CF24504716C885)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |R-Type 2<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Ninja Spirit<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Ganso!! Yancha-Maru<br /> |0x10&ndash;0x13<br /> |-<br /> |0x14<br /> |Match-Mania<br /> |0x14&ndash;0x15<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x16&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === R-Type 2 ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Ninja Spirit ===<br /> <br /> 2000 <= 08 -00 01000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Ganso!! Yancha-Maru ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Match-Mania ===<br /> <br /> 2000 <= 14 -00 10100<br /> 6000 <= 3C -0 1111 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Hudson) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-605)''' (3EB5EBDA098635B2DA0021F46A959DE4)<br /> <br /> PCB: '''DMG-MMM-BEAN-M13'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |GB Genjin<br /> |0x00&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bomber Boy<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Milon Castle<br /> |0x18&ndash;0x1F<br /> |-<br /> |0x20<br /> |Boukenjima 2<br /> |0x20&ndash;0x27<br /> |-<br /> |0x3E<br /> |Menu<br /> |0x3E&ndash;0x3F<br /> |}<br /> ROM banks 0x28&ndash;0x3D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Boukenjima 2 ===<br /> <br /> 2000 <= 20 -01 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === GB Genjin ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 20 -0 1000 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Bomber Boy ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Milon Castle ===<br /> <br /> 2000 <= 18 -00 11000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01_Games&diff=146 MMM01 Games 2019-05-01T17:39:23Z

<p>Tauwasser: /* Mani 4-in-1 (Hudson) */ fix rom list</p> <hr /> <div>__TOC__<br /> <br /> This page lists games that use Nintendo's [[MMM01]], their ROM layout and the configuration settings they use per game.<br /> <br /> = Momotarou Collection 2 =<br /> <br /> ROM: '''Momotarou Collection 2 (Japan)''' (2B589E58D8821C59B7AF702723361DB5)<br /> <br /> PCB: '''DMG-MC-SFCN-01'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Momotarou Dengeki 2<br /> |0x00&ndash;0x1F<br /> |-<br /> |0x20<br /> |Momotarou Gaiden<br /> |0x20&ndash;0x2F<br /> |-<br /> |0x3E<br /> |Menu<br /> |0x3E&ndash;0x3F<br /> |}<br /> <br /> ROM banks 0x30&ndash;0x3D are unused and filled with 0xFF.<br /> <br /> == Settings ==<br /> <br /> === Momotarou Gaiden ===<br /> <br /> 3FFF <= 20 -01 00000<br /> 5FFF <= 40 -1 0000 00<br /> 7FFF <= 21 -0 1000 01<br /> 1FFF <= 3A -0 11 1010<br /> 1FFF <= 7A -1 11 1010<br /> <br /> === Momotarou Dengeki 2 ===<br /> <br /> 3FFF <= 00 -00 00000<br /> 5FFF <= 01 -0 0000 01<br /> 7FFF <= 01 -0 0000 01<br /> 1FFF <= 3A -0 11 1010<br /> 7FFF <= 7A -1 11 1010<br /> <br /> = Taito Variety Pack =<br /> <br /> ROM: '''Taito Variety Pack (Japan)''' (FC84B2E016917D5B0E7DE412D9F8C269)<br /> <br /> PCB: '''DMG-M-PEAN-10'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Sagaia<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Chase H.Q.<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bubble Bobble<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Elevator Action<br /> |0x18&ndash;0x1B<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x1C&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Bubble Bobble ===<br /> <br /> 2000 <= 70 -11 10000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Elevator Action ===<br /> <br /> 2000 <= 78 -11 11000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Chase H.Q. ===<br /> <br /> 2000 <= 68 -11 01000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Sagaia ===<br /> <br /> 2000 <= 60 -11 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Taito) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-602)''' (D57F73C47ACA3E22F4EA2143469AB20E)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> This is the [[#Taito Variety Pack]] released by Mani in China with a different menu.<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Sagaia<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Chase H.Q.<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bubble Bobble<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Elevator Action<br /> |0x18&ndash;0x1B<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x1C&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Bubble Bobble ===<br /> <br /> 2000 <= 70 -11 10000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Elevator Action ===<br /> <br /> 2000 <= 78 -11 11000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Chase H.Q. ===<br /> <br /> 2000 <= 68 -11 01000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Sagaia ===<br /> <br /> 2000 <= 60 -11 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Tomy) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-603)''' (D9293475642991E942AC11262D8E5927)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Ganbaruga<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Esparks<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Raijinou<br /> |0x10&ndash;0x13<br /> |-<br /> |0x14<br /> |Zoids<br /> |0x14&ndash;0x17<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x18&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Ganbaruga ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Raijinou ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Zoids ===<br /> <br /> 2000 <= 14 -00 10100<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Esparks ===<br /> <br /> 2000 <= 08 -00 01000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (irem) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-604)''' (203FD4178EE332D1B2CF24504716C885)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |R-Type 2<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Ninja Spirit<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Ganso!! Yancha-Maru<br /> |0x10&ndash;0x13<br /> |-<br /> |0x14<br /> |Match-Mania<br /> |0x14&ndash;0x15<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x16&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === R-Type 2 ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Ninja Spirit ===<br /> <br /> 2000 <= 08 -00 01000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Ganso!! Yancha-Maru ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Match-Mania ===<br /> <br /> 2000 <= 14 -00 10100<br /> 6000 <= 3C -0 1111 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Hudson) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-605)''' (3EB5EBDA098635B2DA0021F46A959DE4)<br /> <br /> PCB: '''DMG-MMM-BEAN-M13'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |GB Genjin<br /> |0x00&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bomber Boy<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Milon Castle<br /> |0x18&ndash;0x1F<br /> |-<br /> |0x20<br /> |Boukenjima 2<br /> |0x20&ndash;0x27<br /> |-<br /> |0x3E<br /> |Menu<br /> |0x3E&ndash;0x3F<br /> |}<br /> ROM banks 0x28&ndash;0x3D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Boukenjima 2 ===<br /> <br /> 2000 <= 20 -01 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === GB Genjin ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 20 -0 1000 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Bomber Boy ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Milon Castle ===<br /> <br /> 2000 <= 18 -00 11000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01_Games&diff=145 MMM01 Games 2019-05-01T17:38:09Z

<p>Tauwasser: add documentation for MMM01 games</p> <hr /> <div>__TOC__<br /> <br /> This page lists games that use Nintendo's [[MMM01]], their ROM layout and the configuration settings they use per game.<br /> <br /> = Momotarou Collection 2 =<br /> <br /> ROM: '''Momotarou Collection 2 (Japan)''' (2B589E58D8821C59B7AF702723361DB5)<br /> <br /> PCB: '''DMG-MC-SFCN-01'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Momotarou Dengeki 2<br /> |0x00&ndash;0x1F<br /> |-<br /> |0x20<br /> |Momotarou Gaiden<br /> |0x20&ndash;0x2F<br /> |-<br /> |0x3E<br /> |Menu<br /> |0x3E&ndash;0x3F<br /> |}<br /> <br /> ROM banks 0x30&ndash;0x3D are unused and filled with 0xFF.<br /> <br /> == Settings ==<br /> <br /> === Momotarou Gaiden ===<br /> <br /> 3FFF <= 20 -01 00000<br /> 5FFF <= 40 -1 0000 00<br /> 7FFF <= 21 -0 1000 01<br /> 1FFF <= 3A -0 11 1010<br /> 1FFF <= 7A -1 11 1010<br /> <br /> === Momotarou Dengeki 2 ===<br /> <br /> 3FFF <= 00 -00 00000<br /> 5FFF <= 01 -0 0000 01<br /> 7FFF <= 01 -0 0000 01<br /> 1FFF <= 3A -0 11 1010<br /> 7FFF <= 7A -1 11 1010<br /> <br /> = Taito Variety Pack =<br /> <br /> ROM: '''Taito Variety Pack (Japan)''' (FC84B2E016917D5B0E7DE412D9F8C269)<br /> <br /> PCB: '''DMG-M-PEAN-10'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Sagaia<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Chase H.Q.<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bubble Bobble<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Elevator Action<br /> |0x18&ndash;0x1B<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x1C&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Bubble Bobble ===<br /> <br /> 2000 <= 70 -11 10000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Elevator Action ===<br /> <br /> 2000 <= 78 -11 11000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Chase H.Q. ===<br /> <br /> 2000 <= 68 -11 01000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Sagaia ===<br /> <br /> 2000 <= 60 -11 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Taito) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-602)''' (D57F73C47ACA3E22F4EA2143469AB20E)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> This is the [[#Taito Variety Pack]] released by Mani in China with a different menu.<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Sagaia<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Chase H.Q.<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bubble Bobble<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Elevator Action<br /> |0x18&ndash;0x1B<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x1C&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Bubble Bobble ===<br /> <br /> 2000 <= 70 -11 10000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Elevator Action ===<br /> <br /> 2000 <= 78 -11 11000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Chase H.Q. ===<br /> <br /> 2000 <= 68 -11 01000 <br /> 6000 <= 30 -0 1100 00 <br /> 4000 <= 70 -1 1100 00 <br /> 0000 <= 40 -1 00 0000 <br /> <br /> === Sagaia ===<br /> <br /> 2000 <= 60 -11 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 70 -1 1100 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Tomy) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-603)''' (D9293475642991E942AC11262D8E5927)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |Ganbaruga<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Esparks<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Raijinou<br /> |0x10&ndash;0x13<br /> |-<br /> |0x14<br /> |Zoids<br /> |0x14&ndash;0x17<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x18&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Ganbaruga ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Raijinou ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Zoids ===<br /> <br /> 2000 <= 14 -00 10100<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Esparks ===<br /> <br /> 2000 <= 08 -00 01000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (irem) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-604)''' (203FD4178EE332D1B2CF24504716C885)<br /> <br /> PCB: '''DMG-MMM-BEAN-M11'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |R-Type 2<br /> |0x00&ndash;0x07<br /> |-<br /> |0x08<br /> |Ninja Spirit<br /> |0x08&ndash;0x0F<br /> |-<br /> |0x10<br /> |Ganso!! Yancha-Maru<br /> |0x10&ndash;0x13<br /> |-<br /> |0x14<br /> |Match-Mania<br /> |0x14&ndash;0x15<br /> |-<br /> |0x1E<br /> |Menu<br /> |0x1E&ndash;0x1F<br /> |}<br /> ROM banks 0x16&ndash;0x1D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === R-Type 2 ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Ninja Spirit ===<br /> <br /> 2000 <= 08 -00 01000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Ganso!! Yancha-Maru ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 38 -0 1110 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Match-Mania ===<br /> <br /> 2000 <= 14 -00 10100<br /> 6000 <= 3C -0 1111 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> = Mani 4-in-1 (Hudson) =<br /> <br /> ROM: '''Mani 4 in 1 (China) (DMG-605)''' (3EB5EBDA098635B2DA0021F46A959DE4)<br /> <br /> PCB: '''DMG-MMM-BEAN-M13'''<br /> <br /> {| class="wikitable" style="margin:1em auto; width: 50%;"<br /> !style="width: 20%;" | Base Bank<br /> !style="width: 50%;" | ROM<br /> !style="width: 30%;" | Banks Used<br /> |-<br /> |0x00<br /> |GB Genjin<br /> |0x00&ndash;0x0F<br /> |-<br /> |0x10<br /> |Bomber Boy<br /> |0x10&ndash;0x17<br /> |-<br /> |0x18<br /> |Milon Castle<br /> |0x18&ndash;0x1F<br /> |-<br /> |0x20<br /> |Match-Mania<br /> |0x20&ndash;0x27<br /> |-<br /> |0x3E<br /> |Menu<br /> |0x3E&ndash;0x3F<br /> |}<br /> ROM banks 0x28&ndash;0x3D are unused and filled with 0x00.<br /> <br /> == Settings ==<br /> <br /> === Boukenjima 2 ===<br /> <br /> 2000 <= 20 -01 00000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === GB Genjin ===<br /> <br /> 2000 <= 00 -00 00000<br /> 6000 <= 20 -0 1000 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Bomber Boy ===<br /> <br /> 2000 <= 10 -00 10000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> === Milon Castle ===<br /> <br /> 2000 <= 18 -00 11000<br /> 6000 <= 30 -0 1100 00<br /> 4000 <= 40 -1 0000 00<br /> 0000 <= 40 -1 00 0000<br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01&diff=144 MMM01 2019-05-01T16:05:24Z

<p>Tauwasser: correct pin 16 number</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MMM01 can be used to address up to 64&nbsp;Mbit of ROM and 1&nbsp;Mbit of SRAM depending on the mode MMM01 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MMM01 Pinout.png|center|x500px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;11<br /> |D6&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |1<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |13&ndash;15<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |16, 29, 27, 21&ndash;17, 22<br /> |RA22&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |26&ndash;23<br /> |AA16&ndash;AA13<br /> |O<br /> |Upper RAM Address Lines<br /> |-<br /> |32<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |-<br /> |31<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |30<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |}<br /> <br /> Footprint: QFP80P900X900-32<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. D6..D0, A15..A13, {{Overline|RD}}, {{Overline|WR}}, {{Overline|CS}} are internally pulled down with ~50&nbsp;kΩ<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \_________/<br /> | | \-------- RAM Enable<br /> | \----------------- Ram Bank #WE AA14..AA13<br /> \--------------------- Map Enable<br /> <br /> </pre><br /> <br /> * '''RAM Enable''': A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> * '''RAM Bank #WE''': Low-Active Write-Enable lines for the two least-significant RAM bank bits in [[#RAM Bank Register]]. Can only be written when '''Map Enable''' is reset.<br /> * '''Map Enable''': Setting this bit will disable write access to special register bits and disable the forced ROM Address line masking. Can only be written when '''Map Enable''' is reset.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \___/ \____________/<br /> | \-------- ROM Bank RA18..RA14<br /> \-------------------- ROM Bank RA20..RA19<br /> <br /> </pre><br /> <br /> * '''ROM Bank RA18..RA14''': These bits select the lower ROM address lines. The written value is zero-adjusted before output on RA18&ndash;RA14 based only on bits not masked by ROM Bank #WE/Mask RA18..RA15 in [[#Mode Register]].<br /> * '''ROM Bank RA20..RA19''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \___/ \___/<br /> | | | \----- RAM Bank AA14..AA13<br /> | | \----------- RAM Bank AA16..AA15<br /> | \----------------- ROM Bank RA22..RA21<br /> \--------------------- MBC1 Mode #WE<br /> <br /> </pre><br /> <br /> * '''RAM Bank AA14..AA13''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. The MBC1 mode settings still apply, see [[#Mode Register]].<br /> * '''RAM Bank AA16..AA15''': These bits select the upper RAM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''ROM Bank RA22..RA21''': These bits select the upper ROM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''MBC1 Mode #WE''': Low-Active Write Enable for MBC1 Mode in [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \_________/ | |<br /> | | | \--- MBC1 Mode<br /> | | \------ Unknown<br /> | \-------------- ROM Bank #WE/Mask RA18..RA15<br /> \--------------------- Multiplexer for AA14..AA13 and RA20..RA19<br /> <br /> </pre><br /> <br /> * '''MBC1 Mode''': Selects the MBC1 operating mode. 0 for 16&nbsp;Mbit/64&nbsp;kbit mode and 1 for 4&nbsp;MBit/256&nbsp;kbit. Can only be written when '''MBC1 Mode #WE''' in [[#RAM Bank Register]] is reset.<br /> * '''Unknown''': Setting or resetting this bit had no observable effect.<br /> * '''ROM Bank #WE/Mask RA18..RA15''': Low-Active Write-Enable for RA18..RA15 in [[#ROM Bank Register]] as well as mask for zero-adjusting RA18..RA15. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''Multiplexer''': The multiplexer will switch the bits output to pins AA14..AA13 and RA20..RA19. Barring MBC1 Mode logic: when reset, pins will be driven from register contents; when set, pins will be driven from the other register, i.e. RA20..RA19 will be driven by [[#RAM Bank Register]] and AA14..AA13 will be driven by [[#ROM Bank Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> = Operation =<br /> <br /> Operating the MMM01 can be quite complex and the register contents are not straightforward. This section will detail the programming model and give example configurations.<br /> <br /> == Modes of Operation ==<br /> <br /> Nintendo's MMM01 has two modes of operation ''mapped'' and ''unmapped''. It defaults to ''unmapped'' after reset.<br /> <br /> In ''unmapped'' state, the upper ROM address lines RA22..RA15 are all forced to 1, meaning the ROM entry point will be in ROM bank 0x1FE with the only other accessible ROM bank being 0x1FF.<br /> <br /> This is used to lock write access to the upper bits of the known [[MBC1]] registers after base ROM and RAM banks and masks have been set up.<br /> <br /> The only way to ''unmap'' the mapper after ''mapping'' is to reset it.<br /> <br /> == Programming Model ==<br /> <br /> All registers are live, e.g. Setting the RAM Bank #WE bits and subsequently writing to RAM Bank AA14..AA13 won't work -- no matter if in ''mapped'' of ''unmapped'' state. Therefore, there is a certain order in which registers are optimally written:<br /> <br /> # ROM Bank Register<br /> # Mode Register<br /> # RAM Register<br /> # RAM Enable<br /> <br /> Not all of Nintendo's games that use MMM01 keep with this order. However, due to the individual games' sizes and use of RAM banks, this isn't noticeable when the games don't misbehave.<br /> <br /> Most Rom Address line changes cannot be observed in ''unmapped'' mode due to the mapper starting at ROM bank 0x1FE and 0x1FF (depending on A14) until ''mapped''.<br /> <br /> == Map MBC1 Mode 0: 16&nbsp;Mbit/64&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "0", Mux = "1"<br /> <br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (common) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (uncommon) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "1"<br /> <br /> This is probably not the intended use case.<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/256&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> = Remarks =<br /> <br /> == Unknown Bit ==<br /> <br /> There is an Unknown bit in [[#Mode Register]] whose use -- if any -- could not be determined through testing. It is definitely not ROM Bank RA14 #WE as RA14 can be written at all times -- hence there cannot be a single bank mapped to both regions. It might be part of ROM Bank RA14 Mask and an Engineer might have missed that the zero-adjustment logic means that this bit is not necessary.<br /> <br /> == SRAM Enable/Disable ==<br /> <br /> The most glaringly missing feature of MMM01 is an option to disable SRAM access for individual games. The Unknown bit in [[#Mode Register]] does not provide for this either. The only commercial cartridge containing MMM01 and SRAM is Momotarou Collection 2 and it sacrifices one RAM bank to make sure that one game has no chance of deleting the other's save file.<br /> <br /> Having to spend 64&nbsp;kBit to ''disable'' SRAM access seems like a waste considering a simple OR-gate could have stopped SRAM access.<br /> <br /> == Separate MBC1 Mode #WE ==<br /> <br /> The MBC1 Mode #WE stands out as being separated from mapping logic. Instead, if its #WE is not deasserted, it can be freely written even in mapped mode. However, the address line multiplexing for 16&nbsp;Mbit and 4&nbsp;Mbit does not switch with the mode setting -- which given a fixed ROM/SRAM wiring on the cartridge -- would need to be done in order for a hypothetical 16&nbsp;Mbit/256&nbsp;kBit mode to be feasible.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MMM01 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(6 downto 0);<br /> RA : out std_logic_vector(22 downto 14);<br /> AA : out std_logic_vector(16 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MMM01;<br /> <br /> architecture Behavioral of MMM01 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal ram_bank_we_n_r : std_logic_vector(1 downto 0);<br /> signal latch_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_r : std_logic_vector(8 downto 0);<br /> signal ram_bank_r : std_logic_vector(3 downto 0);<br /> signal mode_we_n_r : std_logic_vector(6 downto 6);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_we_n_r : std_logic_vector(4 downto 1);<br /> signal mux_r : std_logic_vector(0 downto 0);<br /> <br /> signal ra_int : std_logic_vector(4 downto 0);<br /> signal aa_int : std_logic_vector(1 downto 0);<br /> <br /> signal ra_lo : std_logic_vector(4 downto 0);<br /> signal ra_mask : std_logic_vector(4 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> alias rom_bank_r_lo : std_logic_vector(4 downto 0) is rom_bank_r(4 downto 0);<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when (A(15) = '0' and RD_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> ra_lo <= "11110" when (latch_r = "0") else<br /> rom_bank_r_lo;<br /> <br /> ra_mask <= "11110" when (latch_r = "0") else<br /> rom_bank_we_n_r & "0";<br /> <br /> ra_int <= "00000" when (A(14) = '0') else<br /> ra_lo when ((ra_lo and not(ra_mask)) /= "00000") else<br /> "00001";<br /> <br /> aa_int <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r(1 downto 0);<br /> <br /> AA(16 downto 15) <= ram_bank_r(3 downto 2);<br /> AA(14 downto 13) <= aa_int when (mux_r = "0") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(22 downto 21) <= "11" when (latch_r = "0") else<br /> rom_bank_r(8 downto 7);<br /> <br /> RA(20 downto 19) <= "11" when (latch_r = "0") else<br /> aa_int when (mux_r = "1") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(18 downto 14) <= (ra_lo and ra_mask) or (ra_int and not(ra_mask));<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> ram_bank_we_n_r <= "00";<br /> latch_r <= "0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> if (latch_r = "0") then<br /> ram_bank_we_n_r <= D(5 downto 4);<br /> latch_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r(6 downto 0) <= "0000000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r(0) <= D(0);<br /> <br /> for i in rom_bank_we_n_r'range loop<br /> if (rom_bank_we_n_r(i) = '0') then<br /> rom_bank_r_lo(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> rom_bank_r(6 downto 5) <= D(6 downto 5);<br /> end if;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "0000";<br /> rom_bank_r(8 downto 7) <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> for i in ram_bank_we_n_r'range loop<br /> if (ram_bank_we_n_r(i) = '0') then<br /> ram_bank_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> ram_bank_r(3 downto 2) <= D(3 downto 2);<br /> rom_bank_r(8 downto 7) <= D(5 downto 4);<br /> mode_we_n_r <= D(6 downto 6);<br /> end if;<br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> rom_bank_we_n_r <= "0000";<br /> mux_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> for i in mode_we_n_r'range loop<br /> if (mode_we_n_r(i) = '0') then<br /> mode_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "1") then<br /> rom_bank_we_n_r <= D(5 downto 2);<br /> mux_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=File:MMM01_Pinout.png&diff=143 File:MMM01 Pinout.png 2019-05-01T16:04:55Z

<p>Tauwasser: Tauwasser uploaded a new version of File:MMM01 Pinout.png</p> <hr /> <div>Pinout for Nintendo's MMM01.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Game_Boy_Dumping_Misc&diff=142 Game Boy Dumping Misc 2018-11-13T22:28:25Z

<p>Tauwasser: redump confirmed missing ル</p> <hr /> <div>== Nikkan Berutomo Club ==<br /> <br /> Nikkan Berutomo Club's name entry screen katakana contains ロ (katakana RO) twice, ル (katakana RU) is missing in right-most column.<br /> Change 2:5163 to 0x83 to rectify this. Apparently the developers just screwed up.<br /> <br /> <gallery widths=160px heights=144px><br /> DMG_Nikkan_Berutomo_Club_Name_Entry_Before.png|Before<br /> DMG_Nikkan_Berutomo_Club_Name_Entry_After.png|After<br /> </gallery><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01&diff=141 MMM01 2018-08-30T18:31:06Z

<p>Tauwasser: /* Modes of Operation */</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MMM01 can be used to address up to 64&nbsp;Mbit of ROM and 1&nbsp;Mbit of SRAM depending on the mode MMM01 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MMM01 Pinout.png|center|x500px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;11<br /> |D6&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |1<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |13&ndash;15<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |15, 29, 27, 21&ndash;17, 22<br /> |RA22&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |26&ndash;23<br /> |AA16&ndash;AA13<br /> |O<br /> |Upper RAM Address Lines<br /> |-<br /> |32<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |-<br /> |31<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |30<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |}<br /> <br /> Footprint: QFP80P900X900-32<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. D6..D0, A15..A13, {{Overline|RD}}, {{Overline|WR}}, {{Overline|CS}} are internally pulled down with ~50&nbsp;kΩ<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \_________/<br /> | | \-------- RAM Enable<br /> | \----------------- Ram Bank #WE AA14..AA13<br /> \--------------------- Map Enable<br /> <br /> </pre><br /> <br /> * '''RAM Enable''': A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> * '''RAM Bank #WE''': Low-Active Write-Enable lines for the two least-significant RAM bank bits in [[#RAM Bank Register]]. Can only be written when '''Map Enable''' is reset.<br /> * '''Map Enable''': Setting this bit will disable write access to special register bits and disable the forced ROM Address line masking. Can only be written when '''Map Enable''' is reset.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \___/ \____________/<br /> | \-------- ROM Bank RA18..RA14<br /> \-------------------- ROM Bank RA20..RA19<br /> <br /> </pre><br /> <br /> * '''ROM Bank RA18..RA14''': These bits select the lower ROM address lines. The written value is zero-adjusted before output on RA18&ndash;RA14 based only on bits not masked by ROM Bank #WE/Mask RA18..RA15 in [[#Mode Register]].<br /> * '''ROM Bank RA20..RA19''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \___/ \___/<br /> | | | \----- RAM Bank AA14..AA13<br /> | | \----------- RAM Bank AA16..AA15<br /> | \----------------- ROM Bank RA22..RA21<br /> \--------------------- MBC1 Mode #WE<br /> <br /> </pre><br /> <br /> * '''RAM Bank AA14..AA13''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. The MBC1 mode settings still apply, see [[#Mode Register]].<br /> * '''RAM Bank AA16..AA15''': These bits select the upper RAM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''ROM Bank RA22..RA21''': These bits select the upper ROM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''MBC1 Mode #WE''': Low-Active Write Enable for MBC1 Mode in [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \_________/ | |<br /> | | | \--- MBC1 Mode<br /> | | \------ Unknown<br /> | \-------------- ROM Bank #WE/Mask RA18..RA15<br /> \--------------------- Multiplexer for AA14..AA13 and RA20..RA19<br /> <br /> </pre><br /> <br /> * '''MBC1 Mode''': Selects the MBC1 operating mode. 0 for 16&nbsp;Mbit/64&nbsp;kbit mode and 1 for 4&nbsp;MBit/256&nbsp;kbit. Can only be written when '''MBC1 Mode #WE''' in [[#RAM Bank Register]] is reset.<br /> * '''Unknown''': Setting or resetting this bit had no observable effect.<br /> * '''ROM Bank #WE/Mask RA18..RA15''': Low-Active Write-Enable for RA18..RA15 in [[#ROM Bank Register]] as well as mask for zero-adjusting RA18..RA15. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''Multiplexer''': The multiplexer will switch the bits output to pins AA14..AA13 and RA20..RA19. Barring MBC1 Mode logic: when reset, pins will be driven from register contents; when set, pins will be driven from the other register, i.e. RA20..RA19 will be driven by [[#RAM Bank Register]] and AA14..AA13 will be driven by [[#ROM Bank Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> = Operation =<br /> <br /> Operating the MMM01 can be quite complex and the register contents are not straightforward. This section will detail the programming model and give example configurations.<br /> <br /> == Modes of Operation ==<br /> <br /> Nintendo's MMM01 has two modes of operation ''mapped'' and ''unmapped''. It defaults to ''unmapped'' after reset.<br /> <br /> In ''unmapped'' state, the upper ROM address lines RA22..RA15 are all forced to 1, meaning the ROM entry point will be in ROM bank 0x1FE with the only other accessible ROM bank being 0x1FF.<br /> <br /> This is used to lock write access to the upper bits of the known [[MBC1]] registers after base ROM and RAM banks and masks have been set up.<br /> <br /> The only way to ''unmap'' the mapper after ''mapping'' is to reset it.<br /> <br /> == Programming Model ==<br /> <br /> All registers are live, e.g. Setting the RAM Bank #WE bits and subsequently writing to RAM Bank AA14..AA13 won't work -- no matter if in ''mapped'' of ''unmapped'' state. Therefore, there is a certain order in which registers are optimally written:<br /> <br /> # ROM Bank Register<br /> # Mode Register<br /> # RAM Register<br /> # RAM Enable<br /> <br /> Not all of Nintendo's games that use MMM01 keep with this order. However, due to the individual games' sizes and use of RAM banks, this isn't noticeable when the games don't misbehave.<br /> <br /> Most Rom Address line changes cannot be observed in ''unmapped'' mode due to the mapper starting at ROM bank 0x1FE and 0x1FF (depending on A14) until ''mapped''.<br /> <br /> == Map MBC1 Mode 0: 16&nbsp;Mbit/64&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "0", Mux = "1"<br /> <br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (common) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (uncommon) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "1"<br /> <br /> This is probably not the intended use case.<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/256&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> = Remarks =<br /> <br /> == Unknown Bit ==<br /> <br /> There is an Unknown bit in [[#Mode Register]] whose use -- if any -- could not be determined through testing. It is definitely not ROM Bank RA14 #WE as RA14 can be written at all times -- hence there cannot be a single bank mapped to both regions. It might be part of ROM Bank RA14 Mask and an Engineer might have missed that the zero-adjustment logic means that this bit is not necessary.<br /> <br /> == SRAM Enable/Disable ==<br /> <br /> The most glaringly missing feature of MMM01 is an option to disable SRAM access for individual games. The Unknown bit in [[#Mode Register]] does not provide for this either. The only commercial cartridge containing MMM01 and SRAM is Momotarou Collection 2 and it sacrifices one RAM bank to make sure that one game has no chance of deleting the other's save file.<br /> <br /> Having to spend 64&nbsp;kBit to ''disable'' SRAM access seems like a waste considering a simple OR-gate could have stopped SRAM access.<br /> <br /> == Separate MBC1 Mode #WE ==<br /> <br /> The MBC1 Mode #WE stands out as being separated from mapping logic. Instead, if its #WE is not deasserted, it can be freely written even in mapped mode. However, the address line multiplexing for 16&nbsp;Mbit and 4&nbsp;Mbit does not switch with the mode setting -- which given a fixed ROM/SRAM wiring on the cartridge -- would need to be done in order for a hypothetical 16&nbsp;Mbit/256&nbsp;kBit mode to be feasible.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MMM01 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(6 downto 0);<br /> RA : out std_logic_vector(22 downto 14);<br /> AA : out std_logic_vector(16 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MMM01;<br /> <br /> architecture Behavioral of MMM01 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal ram_bank_we_n_r : std_logic_vector(1 downto 0);<br /> signal latch_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_r : std_logic_vector(8 downto 0);<br /> signal ram_bank_r : std_logic_vector(3 downto 0);<br /> signal mode_we_n_r : std_logic_vector(6 downto 6);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_we_n_r : std_logic_vector(4 downto 1);<br /> signal mux_r : std_logic_vector(0 downto 0);<br /> <br /> signal ra_int : std_logic_vector(4 downto 0);<br /> signal aa_int : std_logic_vector(1 downto 0);<br /> <br /> signal ra_lo : std_logic_vector(4 downto 0);<br /> signal ra_mask : std_logic_vector(4 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> alias rom_bank_r_lo : std_logic_vector(4 downto 0) is rom_bank_r(4 downto 0);<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when (A(15) = '0' and RD_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> ra_lo <= "11110" when (latch_r = "0") else<br /> rom_bank_r_lo;<br /> <br /> ra_mask <= "11110" when (latch_r = "0") else<br /> rom_bank_we_n_r & "0";<br /> <br /> ra_int <= "00000" when (A(14) = '0') else<br /> ra_lo when ((ra_lo and not(ra_mask)) /= "00000") else<br /> "00001";<br /> <br /> aa_int <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r(1 downto 0);<br /> <br /> AA(16 downto 15) <= ram_bank_r(3 downto 2);<br /> AA(14 downto 13) <= aa_int when (mux_r = "0") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(22 downto 21) <= "11" when (latch_r = "0") else<br /> rom_bank_r(8 downto 7);<br /> <br /> RA(20 downto 19) <= "11" when (latch_r = "0") else<br /> aa_int when (mux_r = "1") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(18 downto 14) <= (ra_lo and ra_mask) or (ra_int and not(ra_mask));<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> ram_bank_we_n_r <= "00";<br /> latch_r <= "0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> if (latch_r = "0") then<br /> ram_bank_we_n_r <= D(5 downto 4);<br /> latch_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r(6 downto 0) <= "0000000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r(0) <= D(0);<br /> <br /> for i in rom_bank_we_n_r'range loop<br /> if (rom_bank_we_n_r(i) = '0') then<br /> rom_bank_r_lo(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> rom_bank_r(6 downto 5) <= D(6 downto 5);<br /> end if;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "0000";<br /> rom_bank_r(8 downto 7) <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> for i in ram_bank_we_n_r'range loop<br /> if (ram_bank_we_n_r(i) = '0') then<br /> ram_bank_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> ram_bank_r(3 downto 2) <= D(3 downto 2);<br /> rom_bank_r(8 downto 7) <= D(5 downto 4);<br /> mode_we_n_r <= D(6 downto 6);<br /> end if;<br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> rom_bank_we_n_r <= "0000";<br /> mux_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> for i in mode_we_n_r'range loop<br /> if (mode_we_n_r(i) = '0') then<br /> mode_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "1") then<br /> rom_bank_we_n_r <= D(5 downto 2);<br /> mux_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01&diff=140 MMM01 2018-08-30T18:30:42Z

<p>Tauwasser: /* Modes of Operation */ add more info about unmapped state</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MMM01 can be used to address up to 64&nbsp;Mbit of ROM and 1&nbsp;Mbit of SRAM depending on the mode MMM01 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MMM01 Pinout.png|center|x500px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;11<br /> |D6&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |1<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |13&ndash;15<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |15, 29, 27, 21&ndash;17, 22<br /> |RA22&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |26&ndash;23<br /> |AA16&ndash;AA13<br /> |O<br /> |Upper RAM Address Lines<br /> |-<br /> |32<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |-<br /> |31<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |30<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |}<br /> <br /> Footprint: QFP80P900X900-32<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. D6..D0, A15..A13, {{Overline|RD}}, {{Overline|WR}}, {{Overline|CS}} are internally pulled down with ~50&nbsp;kΩ<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \_________/<br /> | | \-------- RAM Enable<br /> | \----------------- Ram Bank #WE AA14..AA13<br /> \--------------------- Map Enable<br /> <br /> </pre><br /> <br /> * '''RAM Enable''': A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> * '''RAM Bank #WE''': Low-Active Write-Enable lines for the two least-significant RAM bank bits in [[#RAM Bank Register]]. Can only be written when '''Map Enable''' is reset.<br /> * '''Map Enable''': Setting this bit will disable write access to special register bits and disable the forced ROM Address line masking. Can only be written when '''Map Enable''' is reset.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \___/ \____________/<br /> | \-------- ROM Bank RA18..RA14<br /> \-------------------- ROM Bank RA20..RA19<br /> <br /> </pre><br /> <br /> * '''ROM Bank RA18..RA14''': These bits select the lower ROM address lines. The written value is zero-adjusted before output on RA18&ndash;RA14 based only on bits not masked by ROM Bank #WE/Mask RA18..RA15 in [[#Mode Register]].<br /> * '''ROM Bank RA20..RA19''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \___/ \___/<br /> | | | \----- RAM Bank AA14..AA13<br /> | | \----------- RAM Bank AA16..AA15<br /> | \----------------- ROM Bank RA22..RA21<br /> \--------------------- MBC1 Mode #WE<br /> <br /> </pre><br /> <br /> * '''RAM Bank AA14..AA13''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. The MBC1 mode settings still apply, see [[#Mode Register]].<br /> * '''RAM Bank AA16..AA15''': These bits select the upper RAM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''ROM Bank RA22..RA21''': These bits select the upper ROM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''MBC1 Mode #WE''': Low-Active Write Enable for MBC1 Mode in [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \_________/ | |<br /> | | | \--- MBC1 Mode<br /> | | \------ Unknown<br /> | \-------------- ROM Bank #WE/Mask RA18..RA15<br /> \--------------------- Multiplexer for AA14..AA13 and RA20..RA19<br /> <br /> </pre><br /> <br /> * '''MBC1 Mode''': Selects the MBC1 operating mode. 0 for 16&nbsp;Mbit/64&nbsp;kbit mode and 1 for 4&nbsp;MBit/256&nbsp;kbit. Can only be written when '''MBC1 Mode #WE''' in [[#RAM Bank Register]] is reset.<br /> * '''Unknown''': Setting or resetting this bit had no observable effect.<br /> * '''ROM Bank #WE/Mask RA18..RA15''': Low-Active Write-Enable for RA18..RA15 in [[#ROM Bank Register]] as well as mask for zero-adjusting RA18..RA15. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''Multiplexer''': The multiplexer will switch the bits output to pins AA14..AA13 and RA20..RA19. Barring MBC1 Mode logic: when reset, pins will be driven from register contents; when set, pins will be driven from the other register, i.e. RA20..RA19 will be driven by [[#RAM Bank Register]] and AA14..AA13 will be driven by [[#ROM Bank Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> = Operation =<br /> <br /> Operating the MMM01 can be quite complex and the register contents are not straightforward. This section will detail the programming model and give example configurations.<br /> <br /> == Modes of Operation ==<br /> <br /> Nintendo's MMM01 has two modes of operation ''mapped'' and ''unmapped''. It defaults to ''unmapped'' after reset.<br /> <br /> In ''unmapped'' state, the upper ROM address lines RA22..RA15 are all forced to '1', meaning the ROM entry point will be in ROM bank 0x1FE with the only other accessible ROM bank being 0x1FF.<br /> <br /> This is used to lock write access to the upper bits of the known [[MBC1]] registers after base ROM and RAM banks and masks have been set up.<br /> <br /> The only way to ''unmap'' the mapper after ''mapping'' is to reset it.<br /> <br /> == Programming Model ==<br /> <br /> All registers are live, e.g. Setting the RAM Bank #WE bits and subsequently writing to RAM Bank AA14..AA13 won't work -- no matter if in ''mapped'' of ''unmapped'' state. Therefore, there is a certain order in which registers are optimally written:<br /> <br /> # ROM Bank Register<br /> # Mode Register<br /> # RAM Register<br /> # RAM Enable<br /> <br /> Not all of Nintendo's games that use MMM01 keep with this order. However, due to the individual games' sizes and use of RAM banks, this isn't noticeable when the games don't misbehave.<br /> <br /> Most Rom Address line changes cannot be observed in ''unmapped'' mode due to the mapper starting at ROM bank 0x1FE and 0x1FF (depending on A14) until ''mapped''.<br /> <br /> == Map MBC1 Mode 0: 16&nbsp;Mbit/64&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "0", Mux = "1"<br /> <br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (common) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (uncommon) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "1"<br /> <br /> This is probably not the intended use case.<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/256&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> = Remarks =<br /> <br /> == Unknown Bit ==<br /> <br /> There is an Unknown bit in [[#Mode Register]] whose use -- if any -- could not be determined through testing. It is definitely not ROM Bank RA14 #WE as RA14 can be written at all times -- hence there cannot be a single bank mapped to both regions. It might be part of ROM Bank RA14 Mask and an Engineer might have missed that the zero-adjustment logic means that this bit is not necessary.<br /> <br /> == SRAM Enable/Disable ==<br /> <br /> The most glaringly missing feature of MMM01 is an option to disable SRAM access for individual games. The Unknown bit in [[#Mode Register]] does not provide for this either. The only commercial cartridge containing MMM01 and SRAM is Momotarou Collection 2 and it sacrifices one RAM bank to make sure that one game has no chance of deleting the other's save file.<br /> <br /> Having to spend 64&nbsp;kBit to ''disable'' SRAM access seems like a waste considering a simple OR-gate could have stopped SRAM access.<br /> <br /> == Separate MBC1 Mode #WE ==<br /> <br /> The MBC1 Mode #WE stands out as being separated from mapping logic. Instead, if its #WE is not deasserted, it can be freely written even in mapped mode. However, the address line multiplexing for 16&nbsp;Mbit and 4&nbsp;Mbit does not switch with the mode setting -- which given a fixed ROM/SRAM wiring on the cartridge -- would need to be done in order for a hypothetical 16&nbsp;Mbit/256&nbsp;kBit mode to be feasible.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MMM01 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(6 downto 0);<br /> RA : out std_logic_vector(22 downto 14);<br /> AA : out std_logic_vector(16 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MMM01;<br /> <br /> architecture Behavioral of MMM01 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal ram_bank_we_n_r : std_logic_vector(1 downto 0);<br /> signal latch_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_r : std_logic_vector(8 downto 0);<br /> signal ram_bank_r : std_logic_vector(3 downto 0);<br /> signal mode_we_n_r : std_logic_vector(6 downto 6);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_we_n_r : std_logic_vector(4 downto 1);<br /> signal mux_r : std_logic_vector(0 downto 0);<br /> <br /> signal ra_int : std_logic_vector(4 downto 0);<br /> signal aa_int : std_logic_vector(1 downto 0);<br /> <br /> signal ra_lo : std_logic_vector(4 downto 0);<br /> signal ra_mask : std_logic_vector(4 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> alias rom_bank_r_lo : std_logic_vector(4 downto 0) is rom_bank_r(4 downto 0);<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when (A(15) = '0' and RD_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> ra_lo <= "11110" when (latch_r = "0") else<br /> rom_bank_r_lo;<br /> <br /> ra_mask <= "11110" when (latch_r = "0") else<br /> rom_bank_we_n_r & "0";<br /> <br /> ra_int <= "00000" when (A(14) = '0') else<br /> ra_lo when ((ra_lo and not(ra_mask)) /= "00000") else<br /> "00001";<br /> <br /> aa_int <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r(1 downto 0);<br /> <br /> AA(16 downto 15) <= ram_bank_r(3 downto 2);<br /> AA(14 downto 13) <= aa_int when (mux_r = "0") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(22 downto 21) <= "11" when (latch_r = "0") else<br /> rom_bank_r(8 downto 7);<br /> <br /> RA(20 downto 19) <= "11" when (latch_r = "0") else<br /> aa_int when (mux_r = "1") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(18 downto 14) <= (ra_lo and ra_mask) or (ra_int and not(ra_mask));<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> ram_bank_we_n_r <= "00";<br /> latch_r <= "0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> if (latch_r = "0") then<br /> ram_bank_we_n_r <= D(5 downto 4);<br /> latch_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r(6 downto 0) <= "0000000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r(0) <= D(0);<br /> <br /> for i in rom_bank_we_n_r'range loop<br /> if (rom_bank_we_n_r(i) = '0') then<br /> rom_bank_r_lo(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> rom_bank_r(6 downto 5) <= D(6 downto 5);<br /> end if;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "0000";<br /> rom_bank_r(8 downto 7) <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> for i in ram_bank_we_n_r'range loop<br /> if (ram_bank_we_n_r(i) = '0') then<br /> ram_bank_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> ram_bank_r(3 downto 2) <= D(3 downto 2);<br /> rom_bank_r(8 downto 7) <= D(5 downto 4);<br /> mode_we_n_r <= D(6 downto 6);<br /> end if;<br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> rom_bank_we_n_r <= "0000";<br /> mux_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> for i in mode_we_n_r'range loop<br /> if (mode_we_n_r(i) = '0') then<br /> mode_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "1") then<br /> rom_bank_we_n_r <= D(5 downto 2);<br /> mux_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC1&diff=139 Sachen MMC1 2018-08-23T14:47:35Z

<p>Tauwasser: /* Pinouts */</p> <hr /> <div>Sachen's MMC1 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinouts =<br /> <br /> <gallery widths="350px" heights="400px" style="text-align: center;"><br /> Image:Sachen MMC1 Pinout.png<br /> Image:Sachen MMC1 Rom Pinout.png<br /> </gallery><br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 15%;" | Pin No. MMC1<br /> !style="width: 15%;" | Pin No. MMC1+ROM<br /> !style="width: 20%;" | Name<br /> !style="width: 5%;" | Type<br /> !style="width: 45%;" | Comment<br /> |-<br /> |1, 36<br /> |1<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |21, 35<br /> |17<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |&mdash;<br /> |7&ndash;8, 26<br /> |GND?<br /> |PWR<br /> |Ground supply or unused pin.<br /> |-<br /> |18&ndash;20, 22&ndash;26<br /> |14&ndash;16, 18&ndash;22<br /> |D0&ndash;D7<br /> |I<br /> |Data Bus<br /> |-<br /> |&mdash;<br /> |25<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |29<br /> |32<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |8<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |2&ndash;6, 32, 7, 28, 30, 9, 33&ndash;34, 27<br /> |13&ndash;9, 6&ndash;4, 29&ndash;28, 24, 27, 3, 30&ndash;31, 23<br /> |A0&ndash;A15<br /> |I<br /> |Address Bus<br /> |-<br /> |40&ndash;37<br /> |&mdash;<br /> |RA0, RA1, RA4, RA6<br /> |O<br /> |Scrambled lower ROM Address Lines<br /> |-<br /> |31<br /> |&mdash;<br /> |RA7<br /> |O<br /> |Lower ROM Address Lines<br /> |-<br /> |31, 17&ndash;10<br /> |&mdash;<br /> |RA14&ndash;RA21<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |&mdash;<br /> |&mdash;<br /> |NC<br /> |N/A<br /> |Not connected.<br /> |}<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC1 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC1 has two modes of operation ''locked'' and ''unlocked''. It defaults to ''locked'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG bootstrap ROM. While ''locked'', the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x31 transitions of A15 from high to low. Starting on the last transition, RA7 will follow A7. All control signals are don't cares for this.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =<br /> <br /> == Integrated ROM ==<br /> <br /> The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.<br /> Depending on the bonded ROM smaller ROMs may have an additional low-active CE line on RA17 or RA18.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC2&diff=138 Sachen MMC2 2018-08-23T14:47:34Z

<p>Tauwasser: /* Pinouts */</p> <hr /> <div>Sachen's MMC2 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinouts =<br /> <br /> <gallery widths="350px" heights="400px" style="text-align: center;"><br /> Image:Sachen MMC2 Pinout.png<br /> Image:Sachen MMC2 Rom PinoutA.png<br /> Image:Sachen MMC2 Rom PinoutB.png<br /> </gallery><br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 15%;" | Pin No. MMC2<br /> !style="width: 15%;" | Pin No. MMC2+ROM A (MMC2+ROM B)<br /> !style="width: 20%;" | Name<br /> !style="width: 5%;" | Type<br /> !style="width: 45%;" | Comment<br /> |-<br /> |1<br /> |1, 36 (34)<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |21, 38<br /> |32 (30)<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |&mdash;<br /> |(30&ndash;31)<br /> |NC?<br /> |N/A<br /> |Unused pin.<br /> |-<br /> |6&ndash;5, 37&ndash;36, 27&ndash;26, 16&ndash;15<br /> |21&ndash;28<br /> |D0&ndash;D7<br /> |I<br /> |Data Bus<br /> |-<br /> |&mdash;<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |18<br /> |2<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |19<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |22<br /> |29<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |35&ndash;32, 28, 25, 31&ndash;29, 24&ndash;23, 20, 17<br /> |5&ndash;20<br /> |A0&ndash;A15<br /> |I<br /> |Address Bus<br /> |-<br /> |4&ndash;2, 40<br /> |&mdash;<br /> |RA0, RA1, RA4, RA6<br /> |O<br /> |Scrambled lower ROM Address Lines<br /> |-<br /> |39<br /> |&mdash;<br /> |RA7<br /> |O<br /> |Lower ROM Address Lines<br /> |-<br /> |14&ndash;7<br /> |35 (33)<br /> |RA14&ndash;RA21 resp. RA19<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |&mdash;<br /> |34&ndash;33 (32&ndash;31)<br /> |OPT1&ndash;OPT2<br /> |I (PD)<br /> |Option Input Pins<br /> |-<br /> |&mdash;<br /> |&mdash;<br /> |NC<br /> |N/A<br /> |Not connected.<br /> |}<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC2 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> Sachen added a detection method for Game Boy Color to successfully perform the logo switch, since the Game Boy Color changed the way the logo is checked.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.<br /> <br /> While in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.<br /> Going from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.<br /> The MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register|#Base ROM Bank Register]] and [[#ROM bank mask register|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =<br /> <br /> == Integrated ROM ==<br /> <br /> The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.<br /> ROM chip enable behavior is: <pre>#ROM_CS = A15 or RA20 or OPT2</pre><br /> The highest address line (RA18) will behave as follows: <pre>RA18 = MMC1_RA18 or OPT1</pre></div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC2&diff=137 Sachen MMC2 2018-08-23T14:45:06Z

<p>Tauwasser: /* Pinouts */ add pinouts</p> <hr /> <div>Sachen's MMC2 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinouts =<br /> <br /> <gallery widths="350px" heights="400px" style="text-align: center;"><br /> Image:Sachen MMC2 Pinout.png<br /> Image:Sachen MMC2 Rom PinoutA.png<br /> Image:Sachen MMC2 Rom PinoutB.png<br /> </gallery><br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 15%;" | Pin No. MMC2<br /> !style="width: 15%;" | Pin No. MMC2+ROM A (MMC2+ROM B)<br /> !style="width: 20%;" | Name<br /> !style="width: 5%;" | Type<br /> !style="width: 45%;" | Comment<br /> |-<br /> |1<br /> |1, 36 (34)<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |21, 38<br /> |32 (30)<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |&mdash;<br /> |(30&ndash;31)<br /> |NC?<br /> |N/A<br /> |Unused pin.<br /> |-<br /> |6&ndash;5, 37&ndash;36, 27&ndash;26, 16&ndash;15<br /> |21&ndash;28<br /> |D0&ndash;D7<br /> |I<br /> |Data Bus<br /> |-<br /> |&mdash;<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |18<br /> |2<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |19<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |22<br /> |29<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |35&ndash;32, 28, 25, 31&ndash;29, 24&ndash;23, 20, 17<br /> |5&ndash;20<br /> |A0&ndash;A15<br /> |I<br /> |Address Bus<br /> |-<br /> |4&ndash;2, 40<br /> |&mdash;<br /> |RA0, RA1, RA4, RA6<br /> |O<br /> |Scrambled lower ROM Address Lines<br /> |-<br /> |39<br /> |&mdash;<br /> |RA7<br /> |O<br /> |Lower ROM Address Lines<br /> |-<br /> |14&ndash;7<br /> |35 (33)<br /> |RA14&ndash;RA21 resp. RA19<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |&mdash;<br /> |34&ndash;33 (32&ndash;31)<br /> |OPT1&ndash;OPT2<br /> |I (PD)<br /> |Option Input Pins<br /> |}<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC2 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> Sachen added a detection method for Game Boy Color to successfully perform the logo switch, since the Game Boy Color changed the way the logo is checked.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.<br /> <br /> While in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.<br /> Going from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.<br /> The MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register|#Base ROM Bank Register]] and [[#ROM bank mask register|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =<br /> <br /> == Integrated ROM ==<br /> <br /> The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.<br /> ROM chip enable behavior is: <pre>#ROM_CS = A15 or RA20 or OPT2</pre><br /> The highest address line (RA18) will behave as follows: <pre>RA18 = MMC1_RA18 or OPT1</pre></div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=File:Sachen_MMC2_Rom_PinoutB.png&diff=136 File:Sachen MMC2 Rom PinoutB.png 2018-08-23T14:32:46Z

<p>Tauwasser: Pinout for Sachen's MMC2 with integrated ROM variant B.</p> <hr /> <div>== Summary ==<br /> Pinout for Sachen's MMC2 with integrated ROM variant B.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=File:Sachen_MMC2_Rom_PinoutA.png&diff=135 File:Sachen MMC2 Rom PinoutA.png 2018-08-23T14:32:33Z

<p>Tauwasser: Pinout for Sachen's MMC2 with integrated ROM variant A.</p> <hr /> <div>== Summary ==<br /> Pinout for Sachen's MMC2 with integrated ROM variant A.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=File:Sachen_MMC2_Pinout.png&diff=134 File:Sachen MMC2 Pinout.png 2018-08-23T14:32:02Z

<p>Tauwasser: Pinout for Sachen's MMC2.</p> <hr /> <div>== Summary ==<br /> Pinout for Sachen's MMC2.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC2&diff=133 Sachen MMC2 2018-08-23T14:30:41Z

<p>Tauwasser: /* Behavior */ document ROM behavior</p> <hr /> <div>Sachen's MMC2 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinout =<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC2 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> Sachen added a detection method for Game Boy Color to successfully perform the logo switch, since the Game Boy Color changed the way the logo is checked.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.<br /> <br /> While in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.<br /> Going from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.<br /> The MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register|#Base ROM Bank Register]] and [[#ROM bank mask register|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =<br /> <br /> == Integrated ROM ==<br /> <br /> The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.<br /> ROM chip enable behavior is: <pre>#ROM_CS = A15 or RA20 or OPT2</pre><br /> The highest address line (RA18) will behave as follows: <pre>RA18 = MMC1_RA18 or OPT1</pre></div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC1&diff=132 Sachen MMC1 2018-08-23T14:26:32Z

<p>Tauwasser: /* Behavior */</p> <hr /> <div>Sachen's MMC1 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinouts =<br /> <br /> <gallery widths="350px" heights="400px" style="text-align: center;"><br /> Image:Sachen MMC1 Pinout.png<br /> Image:Sachen MMC1 Rom Pinout.png<br /> </gallery><br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 15%;" | Pin No. MMC1<br /> !style="width: 15%;" | Pin No. MMC1+ROM<br /> !style="width: 20%;" | Name<br /> !style="width: 5%;" | Type<br /> !style="width: 45%;" | Comment<br /> |-<br /> |1, 36<br /> |1<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |21, 35<br /> |17<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |&mdash;<br /> |7&ndash;8, 26<br /> |GND?<br /> |PWR<br /> |Ground supply or unused pin.<br /> |-<br /> |18&ndash;20, 22&ndash;26<br /> |14&ndash;16, 18&ndash;22<br /> |D0&ndash;D7<br /> |I<br /> |Data Bus<br /> |-<br /> |&mdash;<br /> |25<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |29<br /> |32<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |8<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |2&ndash;6, 32, 7, 28, 30, 9, 33&ndash;34, 27<br /> |13&ndash;9, 6&ndash;4, 29&ndash;28, 24, 27, 3, 30&ndash;31, 23<br /> |A0&ndash;A15<br /> |I<br /> |Address Bus<br /> |-<br /> |40&ndash;37<br /> |&mdash;<br /> |RA0, RA1, RA4, RA6<br /> |O<br /> |Scrambled lower ROM Address Lines<br /> |-<br /> |31<br /> |&mdash;<br /> |RA7<br /> |O<br /> |Lower ROM Address Lines<br /> |-<br /> |31, 17&ndash;10<br /> |&mdash;<br /> |RA14&ndash;RA21<br /> |O<br /> |Upper ROM Address Lines<br /> |}<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC1 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC1 has two modes of operation ''locked'' and ''unlocked''. It defaults to ''locked'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG bootstrap ROM. While ''locked'', the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x31 transitions of A15 from high to low. Starting on the last transition, RA7 will follow A7. All control signals are don't cares for this.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =<br /> <br /> == Integrated ROM ==<br /> <br /> The integrated ROM behaves as a regular ROM chip that's connected to the An resp. RAn address and Dn data lines.<br /> Depending on the bonded ROM smaller ROMs may have an additional low-active CE line on RA17 or RA18.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC1&diff=131 Sachen MMC1 2018-08-23T14:22:40Z

<p>Tauwasser: /* Pinouts */</p> <hr /> <div>Sachen's MMC1 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinouts =<br /> <br /> <gallery widths="350px" heights="400px" style="text-align: center;"><br /> Image:Sachen MMC1 Pinout.png<br /> Image:Sachen MMC1 Rom Pinout.png<br /> </gallery><br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 15%;" | Pin No. MMC1<br /> !style="width: 15%;" | Pin No. MMC1+ROM<br /> !style="width: 20%;" | Name<br /> !style="width: 5%;" | Type<br /> !style="width: 45%;" | Comment<br /> |-<br /> |1, 36<br /> |1<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |21, 35<br /> |17<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |&mdash;<br /> |7&ndash;8, 26<br /> |GND?<br /> |PWR<br /> |Ground supply or unused pin.<br /> |-<br /> |18&ndash;20, 22&ndash;26<br /> |14&ndash;16, 18&ndash;22<br /> |D0&ndash;D7<br /> |I<br /> |Data Bus<br /> |-<br /> |&mdash;<br /> |25<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |29<br /> |32<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |8<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |2&ndash;6, 32, 7, 28, 30, 9, 33&ndash;34, 27<br /> |13&ndash;9, 6&ndash;4, 29&ndash;28, 24, 27, 3, 30&ndash;31, 23<br /> |A0&ndash;A15<br /> |I<br /> |Address Bus<br /> |-<br /> |40&ndash;37<br /> |&mdash;<br /> |RA0, RA1, RA4, RA6<br /> |O<br /> |Scrambled lower ROM Address Lines<br /> |-<br /> |31<br /> |&mdash;<br /> |RA7<br /> |O<br /> |Lower ROM Address Lines<br /> |-<br /> |31, 17&ndash;10<br /> |&mdash;<br /> |RA14&ndash;RA21<br /> |O<br /> |Upper ROM Address Lines<br /> |}<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC1 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC1 has two modes of operation ''locked'' and ''unlocked''. It defaults to ''locked'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG bootstrap ROM. While ''locked'', the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x31 transitions of A15 from high to low. Starting on the last transition, RA7 will follow A7. All control signals are don't cares for this.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=File:Sachen_MMC1_Rom_Pinout.png&diff=130 File:Sachen MMC1 Rom Pinout.png 2018-08-23T13:58:47Z

<p>Tauwasser: Pinout for Sachen's MMC1 with integrated ROM.</p> <hr /> <div>== Summary ==<br /> Pinout for Sachen's MMC1 with integrated ROM.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=File:Sachen_MMC1_Pinout.png&diff=129 File:Sachen MMC1 Pinout.png 2018-08-23T13:58:25Z

<p>Tauwasser: Pinout for Sachen's MMC1.</p> <hr /> <div>== Summary ==<br /> Pinout for Sachen's MMC1.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC2&diff=128 Sachen MMC2 2018-08-23T12:24:45Z

<p>Tauwasser: switch Header Scramble and Multi Memory Remap sections</p> <hr /> <div>Sachen's MMC2 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinout =<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC2 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> Sachen added a detection method for Game Boy Color to successfully perform the logo switch, since the Game Boy Color changed the way the logo is checked.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.<br /> <br /> While in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.<br /> Going from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.<br /> The MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register|#Base ROM Bank Register]] and [[#ROM bank mask register|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=127 User:Tauwasser/Sandbox 2018-02-15T23:20:15Z

<p>Tauwasser: Is this real magic?</p> <hr /> <div>What is this popup??<br /> Your edit was saved.<br /> Derp<br /> Narf<br /> Hmm<br /> Check console<br /> Css magic?</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MediaWiki:Common.css&diff=126 MediaWiki:Common.css 2018-02-15T23:19:49Z

<p>Tauwasser: See if this does something</p> <hr /> <div>/* CSS placed here will be applied to all skins */<br /> .pintable td {<br /> text-align: center;<br /> }<br /> .pintable td:nth-child(4) {<br /> text-align: left;<br /> }<br /> <br /> table.wikitable > * > tr > td {<br /> padding: 0.2em 0.4em;<br /> }<br /> <br /> #toc { float: right; }</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=125 User:Tauwasser/Sandbox 2018-02-15T23:14:10Z

<p>Tauwasser: Test</p> <hr /> <div>What is this popup??<br /> Your edit was saved.<br /> Derp<br /> Narf<br /> Hmm<br /> Check console</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=124 User:Tauwasser/Sandbox 2018-02-15T23:07:43Z

<p>Tauwasser: Mark Default Minor</p> <hr /> <div>What is this popup??<br /> Your edit was saved.<br /> Derp<br /> Narf<br /> Hmm</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=123 User:Tauwasser/Sandbox 2018-02-15T23:04:08Z

<p>Tauwasser: Zonk</p> <hr /> <div>What is this popup??<br /> Your edit was saved.<br /> Derp<br /> Narf</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=122 User:Tauwasser/Sandbox 2018-02-15T23:03:51Z

<p>Tauwasser: Hurr</p> <hr /> <div>What is this popup??<br /> Your edit was saved.<br /> Derp</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=121 User:Tauwasser/Sandbox 2018-02-15T22:57:43Z

<p>Tauwasser: Your edit was saved.</p> <hr /> <div>What is this popup??<br /> Your edit was saved.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=120 User:Tauwasser/Sandbox 2018-02-15T22:55:40Z

<p>Tauwasser: adsada</p> <hr /> <div>What is this popup??</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=119 User:Tauwasser/Sandbox 2018-02-15T22:52:25Z

<p>Tauwasser: sdasdasd</p> <hr /> <div>Test<br /> 2</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=User:Tauwasser/Sandbox&diff=118 User:Tauwasser/Sandbox 2018-02-15T22:51:42Z

<p>Tauwasser: Created page with "Test"</p> <hr /> <div>Test</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_Mappers&diff=117 Sachen Mappers 2018-02-15T22:50:42Z

<p>Tauwasser: split pages up</p> <hr /> <div>__TOC__<br /> <br /> Sachen manufactured unlicensed Game Boy and Game Boy Color games from ~2000 until 2007.<br /> <br /> Two Sachen Mappers are thought to exist. Both exist in a stand-alone variant -- just the mapper under glob top -- and an integrated variant -- mapper and ROM are under the same glob top on the PCB.<br /> <br /> {| class="wikitable" style="width: 30%;"<br /> !style="width: 50%;" | Name<br /> !style="width: 50%;" | Comment<br /> |-<br /> |[[Sachen MMC1]]<br /> |MMC for mono 4B games.<br /> |-<br /> |[[Sachen MMC2]]<br /> |MMC for mono/color 1B games.<br /> <br /> MMC for color 4B games.<br /> <br /> MMC for color 6B games.<br /> <br /> MMC for color 8B games.<br /> <br /> MMC for color 16B games.<br /> <br /> MMC for color 31B games.<br /> |}<br /> <br /> = Notes =<br /> <br /> == 0x6000 - 0x7FFF ==<br /> <br /> Writing to the 0x6000-0x7FFF range did not affect mapping in any way. I did an exhaustive test.<br /> <br /> <pre><br /> for (k= 0x0000; k < 0x2000; k++) {<br /> for (l = 0x00; l < 0x100u; l++) {<br /> // reset to base RB 0x00 with mask 0x00 here<br /> <br /> // map RB 0x04 with mask 0xFC<br /> writeb(0x2000u, 0xFFu); // enable map regs<br /> writeb(0x0000u, 0x04u); // base RB<br /> writeb(0x4000u, 0xFCu); // mask<br /> writeb(0x6000 | k, l); // see if this does anything<br /> writeb(0x2000u, 0x00u); // disable map regs<br /> <br /> //check RB 0x00 - RB 0x04 against known hashes and report error<br /> }<br /> }<br /> </pre><br /> <br /> == 0xA000 - 0xBFFF ==<br /> <br /> Reading from this range produced no results.<br /> <br /> = Miscellaneous Information =<br /> <br /> Too bad Sachen screwed up (on 4B-007 at least) and actually writes the base RB to the mask register and the mask to the base RB register, thus all games having broken masking. But due to power-of-2 sizes of RBs and masks, it turns out that only a few extra RBs are mappable which shouldn't be instead of the games skipping ROM banks.<br /> <br /> I noticed that the Sachen logo check -- VRAM comparison of Sachen logo starting at 0x8010 -- was disabled in the mapped games. I also noticed that games do write to 0x0000-0x1FFF while being mapped, so this may have some effect. Technically, since A15..A6, A4, A1, A0 are connected, there might be many registers mapped. Initial tests show this not to be the case.<br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC2&diff=116 Sachen MMC2 2018-02-15T22:48:01Z

<p>Tauwasser: fix relative links</p> <hr /> <div>Sachen's MMC2 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinout =<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC2 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> Sachen added a detection method for Game Boy Color to successfully perform the logo switch, since the Game Boy Color changed the way the logo is checked.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.<br /> <br /> While in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.<br /> Going from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.<br /> The MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register|#Base ROM Bank Register]] and [[#ROM bank mask register|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC2&diff=115 Sachen MMC2 2018-02-15T22:31:22Z

<p>Tauwasser: split into own page</p> <hr /> <div>Sachen's MMC2 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinout =<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC2 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> Sachen added a detection method for Game Boy Color to successfully perform the logo switch, since the Game Boy Color changed the way the logo is checked.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC2 has three modes of operation ''locked DMG'', ''locked CGB'' and ''unlocked''. It defaults to ''locked DMG'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG and CGB bootstrap ROMs. Because the DMG bootstrap copies the logo first and checks after displaying it, while the CGB bootstrap checks first and only afterwards uses the actual logo, Sachen devised a mechanism to detect a CGB using the fact that the CGB bootstrap writes to WRAM, while the DMG bootstrap doesn't.<br /> <br /> While in ''locked DMG'' and ''unlocked'' modes, RA7 will follow A7. While in ''locked CGB'' mode, the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x30 transitions of A15 from low to high to go from ''locked DMG'' mode to ''locked CGB'' mode. Starting on the last transition, RA7 will remain set.<br /> Going from ''locked CGB'' mode to ''unlocked'' mode requires another 0x30 transitions of A15 from low to high. Starting on the last transition, RA7 will follow A7 again.<br /> The MMC2 mapper will skip directly from ''locked DMG'' mode to ''locked CGB'' on a rising edge of CS. The A15 transition counter is reset when changing from ''locked DMG'' to ''locked CGB'' mode.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''.<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register_2|#Base ROM Bank Register]] and [[#ROM bank mask register_2|#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are eight high address lines on the SA8MBT6-2 w/o BAT PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register_2|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register_2|#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Sachen_MMC1&diff=114 Sachen MMC1 2018-02-15T22:26:58Z

<p>Tauwasser: split into own page</p> <hr /> <div>Sachen's MMC1 can be used to address up to 32 Mbit of ROM. It contains provisions for SRAM access.<br /> <br /> = Pinout =<br /> <br /> = Theory of Operation =<br /> <br /> Sachen's MMC1 mappers are used for multi-game N-in-1 cartridges. Individual game ROMs can be remapped so their address space logically starts at ROM bank 0x00 although the individual ROMs might be stored starting at another bank.<br /> To avoid copyright infringement the game headers are scrambled and the mapper unscrambles them when the header region is read. The mapper also includes a mechanism to switch out the Nintendo logo with a custom logo while still passing the Game Boy Bootstrap logo check. All of these features are also used by various games as a copy-protection mechanism, e.g. ROM mapping, unscrambling and the logo in VRAM are checked to determine if the game is run from an original Sachen cartridge.<br /> <br /> == Modes of Operation ==<br /> <br /> Sachen MMC1 has two modes of operation ''locked'' and ''unlocked''. It defaults to ''locked'' after reset.<br /> <br /> This is used to display the Sachen logo instead of the Nintendo logo for the DMG bootstrap ROM. While ''locked'', the mapper will keep RA7 set.<br /> <br /> The unlock sequence is 0x31 transitions of A15 from high to low. Starting on the last transition, RA7 will follow A7. All control signals are don't cares for this.<br /> <br /> Other functionality seems to be unaffected by the lock register: switching banks and remapping work while ''locked''<br /> <br /> The only way to ''lock'' the mapper after ''unlocking'' is to reset it.<br /> <br /> == Header Scramble ==<br /> <br /> Sachen chose to scramble the header of their games. When A8 is high, while A15..A9 are low, the mapper will perform the following map:<br /> <br /> <pre><br /> RA0 <= A6<br /> RA1 <= A4<br /> RA4 <= A1<br /> RA6 <= A0<br /> </pre><br /> <br /> When A8 is low or A15..A9 are not low, RAn lines will track their respective An line.<br /> <br /> == Multi Memory Remap ==<br /> <br /> Base ROM Bank and ROM Bank Mask Register are used for remapping 0x0000-0x7FFF to be based on a new base ROM bank.<br /> <br /> The mapping function is: <pre>(rb & ~mask) | (mask & rb_base)</pre><br /> <br /> = Memory Map =<br /> <br /> * <tt>0x0000-0x3FFF</tt>: Mapped ROM bank #0<br /> * <tt>0x4000-0x7FFF</tt>: Mapped Switchable ROM bank<br /> * <tt>0x8000-0xFFFF</tt>: Unmapped<br /> <br /> Mapped here means adjusted for absolute Base ROM bank.<br /> <br /> The RAn pins depend solely on A14, thus they will alias the <tt>0x0000-0x7FFF</tt> region to <tt>0x8000-0xFFFF</tt>. ROM is still only enabled when A15 is low, so no output is produced.<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: Base ROM bank register<br /> * <tt>0x2000-0x3FFF</tt>: ROM bank register<br /> * <tt>0x4000-0x5FFF</tt>: ROM bank mask register<br /> <br /> == ROM Bank Register ==<br /> <br /> The ROM bank register is zero-adjusted, i.e. if 0x00 is written, 0x01 will be stored. Zero-adjustment is done on all 8 input bits D7..D0. This means, that ROM Bank 0x00 can only be mapped to 0x4000-0x7FFF when the attached ROM is smaller than 32 Mbit and thus aliases 0x80 to 0x00.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x01 @ reset<br /> \_____________________/<br /> \___/ \-------- ROM Bank<br /> |<br /> \----------------- Map Enable<br /> </pre><br /> <br /> ROM Bank bits switch the bank mapped to 0x4000-0x7FFF.<br /> Map Enable bits are used to enable write access to the [[#Base ROM Bank Register]] and [[#ROM bank mask register]]. 0b11 means these registers can be written, other values will not grant write access.<br /> <br /> The width of this register is based off the fact that there are six high address lines, two more landing pads (not bonded) visible and I/O lines numbered (15 next to trace with 13 visible traces) on the 1231 PCB.<br /> <br /> == Base ROM Bank Register ==<br /> <br /> This register stores the base ROM bank.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- Base ROM Bank<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> == ROM bank mask register ==<br /> <br /> This register stores the ROM bank mask.<br /> <br /> <pre><br /> D7 D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \_____________________/<br /> \-------- ROM Bank Mask<br /> </pre><br /> <br /> This register is writable without limitation when Map Enable in the [[#ROM Bank Register]] is 0b11.<br /> Changes to this register take immediate effect.<br /> <br /> = Behavior =</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MBC1&diff=113 MBC1 2017-06-23T20:30:31Z

<p>Tauwasser: /* Mode Register */</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MBC1 can be used to address up to 16&nbsp;Mbit of ROM and 256&nbsp;kbit of SRAM, depending on the mode MBC1 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MBC1 Pinout.png|center|x300px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |24<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;1<br /> |D4&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |11<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |22<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |23<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |10<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |21&ndash;19<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |18&ndash;14<br /> |RA18&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |7&ndash;6<br /> |AA14&ndash;AA13<br /> |O<br /> |Upper ROM/RAM Address Lines<br /> |-<br /> |8<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |9<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |-<br /> |13<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |}<br /> <br /> Footprint: SOP127P1200X225-24<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX XX XX XX D3 D2 D1 D0 0x00 @ reset<br /> \_________/<br /> \-------- RAM Enable<br /> <br /> </pre><br /> <br /> A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX XX XX D4 D3 D2 D1 D0 0x00 @ reset<br /> \____________/<br /> \-------- ROM Bank<br /> <br /> </pre><br /> <br /> ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA18&ndash;RA14.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX XX XX XX XX XX D1 D0 0x00 @ reset<br /> \___/<br /> \----- RAM Bank<br /> <br /> </pre><br /> <br /> RAM Bank selects which bank is mapped to 0xA000-0xBFFF when in mode 4&nbsp;MBit/256&nbsp;kbit. When in mode 16&nbsp;Mbit/64&nbsp;kbit, it can be used to select the upper two ROM address lines.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX XX XX XX XX XX XX D0 0x00 @ reset<br /> |<br /> \--- Mode<br /> <br /> </pre><br /> <br /> The mode bit switches between 16&nbsp;Mbit ROM/64&nbsp;kbit SRAM mode ('0') and 4&nbsp;Mbit ROM/256&nbsp;kbit SRAM mode ('1'). When in 16&nbsp;Mbit/64&nbsp;kbit mode, address lines AA14&ndash;AA13 switch according to A14. When in 4&nbsp;Mbit/256&nbsp;kbit mode, the upper address lines AA14&ndash;AA13 stay fixed regardless of A14.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MBC1 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(4 downto 0);<br /> RA : out std_logic_vector(18 downto 14);<br /> AA : out std_logic_vector(14 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MBC1;<br /> <br /> architecture Behavioral of MBC1 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal rom_bank_r : std_logic_vector(4 downto 0);<br /> signal ram_bank_r : std_logic_vector(1 downto 0);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when ((A(15) = '0' and RD_N = '0') or RESET_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> RA(18 downto 14) <= "00000" when (A(14) = '0' or RESET_N = '0') else<br /> rom_bank_r when (rom_bank_r /= "00000") else<br /> "00001";<br /> <br /> AA(14 downto 13) <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r;<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r <= "00000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r <= D;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> ram_bank_r <= D(1 downto 0);<br /> <br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> mode_r <= D(0 downto 0);<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MMM01&diff=112 MMM01 2017-06-23T17:56:18Z

<p>Tauwasser: add mmm01 information</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MMM01 can be used to address up to 64&nbsp;Mbit of ROM and 1&nbsp;Mbit of SRAM depending on the mode MMM01 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MMM01 Pinout.png|center|x500px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;11<br /> |D6&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |3<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |1<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |4<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |2<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |13&ndash;15<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |15, 29, 27, 21&ndash;17, 22<br /> |RA22&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |26&ndash;23<br /> |AA16&ndash;AA13<br /> |O<br /> |Upper RAM Address Lines<br /> |-<br /> |32<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |-<br /> |31<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |30<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |}<br /> <br /> Footprint: QFP80P900X900-32<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. D6..D0, A15..A13, {{Overline|RD}}, {{Overline|WR}}, {{Overline|CS}} are internally pulled down with ~50&nbsp;kΩ<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \_________/<br /> | | \-------- RAM Enable<br /> | \----------------- Ram Bank #WE AA14..AA13<br /> \--------------------- Map Enable<br /> <br /> </pre><br /> <br /> * '''RAM Enable''': A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> * '''RAM Bank #WE''': Low-Active Write-Enable lines for the two least-significant RAM bank bits in [[#RAM Bank Register]]. Can only be written when '''Map Enable''' is reset.<br /> * '''Map Enable''': Setting this bit will disable write access to special register bits and disable the forced ROM Address line masking. Can only be written when '''Map Enable''' is reset.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> \___/ \____________/<br /> | \-------- ROM Bank RA18..RA14<br /> \-------------------- ROM Bank RA20..RA19<br /> <br /> </pre><br /> <br /> * '''ROM Bank RA18..RA14''': These bits select the lower ROM address lines. The written value is zero-adjusted before output on RA18&ndash;RA14 based only on bits not masked by ROM Bank #WE/Mask RA18..RA15 in [[#Mode Register]].<br /> * '''ROM Bank RA20..RA19''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \___/ \___/ \___/<br /> | | | \----- RAM Bank AA14..AA13<br /> | | \----------- RAM Bank AA16..AA15<br /> | \----------------- ROM Bank RA22..RA21<br /> \--------------------- MBC1 Mode #WE<br /> <br /> </pre><br /> <br /> * '''RAM Bank AA14..AA13''': These bits select the middle ROM address lines '''or''' the lower RAM address lines depending on the multiplex setting in the [[#Mode Register]]. The MBC1 mode settings still apply, see [[#Mode Register]].<br /> * '''RAM Bank AA16..AA15''': These bits select the upper RAM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''ROM Bank RA22..RA21''': These bits select the upper ROM address lines. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''MBC1 Mode #WE''': Low-Active Write Enable for MBC1 Mode in [[#Mode Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX D6 D5 D4 D3 D2 D1 D0 0x00 @ reset<br /> | \_________/ | |<br /> | | | \--- MBC1 Mode<br /> | | \------ Unknown<br /> | \-------------- ROM Bank #WE/Mask RA18..RA15<br /> \--------------------- Multiplexer for AA14..AA13 and RA20..RA19<br /> <br /> </pre><br /> <br /> * '''MBC1 Mode''': Selects the MBC1 operating mode. 0 for 16&nbsp;Mbit/64&nbsp;kbit mode and 1 for 4&nbsp;MBit/256&nbsp;kbit. Can only be written when '''MBC1 Mode #WE''' in [[#RAM Bank Register]] is reset.<br /> * '''Unknown''': Setting or resetting this bit had no observable effect.<br /> * '''ROM Bank #WE/Mask RA18..RA15''': Low-Active Write-Enable for RA18..RA15 in [[#ROM Bank Register]] as well as mask for zero-adjusting RA18..RA15. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> * '''Multiplexer''': The multiplexer will switch the bits output to pins AA14..AA13 and RA20..RA19. Barring MBC1 Mode logic: when reset, pins will be driven from register contents; when set, pins will be driven from the other register, i.e. RA20..RA19 will be driven by [[#RAM Bank Register]] and AA14..AA13 will be driven by [[#ROM Bank Register]]. Can only be written when '''Map Enable''' in [[#RAM Enable Register]] is reset.<br /> <br /> = Operation =<br /> <br /> Operating the MMM01 can be quite complex and the register contents are not straightforward. This section will detail the programming model and give example configurations.<br /> <br /> == Modes of Operation ==<br /> <br /> Nintendo's MMM01 has two modes of operation ''mapped'' and ''unmapped''. It defaults to ''unmapped'' after reset.<br /> <br /> This is used to lock write access to the upper bits of the known [[MBC1]] registers after base ROM and RAM banks and masks have been set up.<br /> <br /> The only way to ''unmap'' the mapper after ''mapping'' is to reset it.<br /> <br /> == Programming Model ==<br /> <br /> All registers are live, e.g. Setting the RAM Bank #WE bits and subsequently writing to RAM Bank AA14..AA13 won't work -- no matter if in ''mapped'' of ''unmapped'' state. Therefore, there is a certain order in which registers are optimally written:<br /> <br /> # ROM Bank Register<br /> # Mode Register<br /> # RAM Register<br /> # RAM Enable<br /> <br /> Not all of Nintendo's games that use MMM01 keep with this order. However, due to the individual games' sizes and use of RAM banks, this isn't noticeable when the games don't misbehave.<br /> <br /> Most Rom Address line changes cannot be observed in ''unmapped'' mode due to the mapper starting at ROM bank 0x1FE and 0x1FF (depending on A14) until ''mapped''.<br /> <br /> == Map MBC1 Mode 0: 16&nbsp;Mbit/64&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "0", Mux = "1"<br /> <br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (common) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/64&nbsp;kBit (uncommon) ==<br /> <br /> * R0: AA #WE = "11"<br /> * R1: RA20..RA19 = fix --> SRAM AA14..AA13 muxed<br /> * R2: AA16..AA13, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "1"<br /> <br /> This is probably not the intended use case.<br /> <br /> == Map MBC1 Mode 1: 4&nbsp;Mbit/256&nbsp;kBit ==<br /> <br /> * R0: AA #WE = "00"<br /> * R1: RA20..RA19 = fix<br /> * R2: AA16..AA15, RA22..RA21 = fix, MBC Mode #WE = "1"<br /> * R3: RA #WE = "0000", Mode = "1", Mux = "0"<br /> <br /> = Remarks =<br /> <br /> == Unknown Bit ==<br /> <br /> There is an Unknown bit in [[#Mode Register]] whose use -- if any -- could not be determined through testing. It is definitely not ROM Bank RA14 #WE as RA14 can be written at all times -- hence there cannot be a single bank mapped to both regions. It might be part of ROM Bank RA14 Mask and an Engineer might have missed that the zero-adjustment logic means that this bit is not necessary.<br /> <br /> == SRAM Enable/Disable ==<br /> <br /> The most glaringly missing feature of MMM01 is an option to disable SRAM access for individual games. The Unknown bit in [[#Mode Register]] does not provide for this either. The only commercial cartridge containing MMM01 and SRAM is Momotarou Collection 2 and it sacrifices one RAM bank to make sure that one game has no chance of deleting the other's save file.<br /> <br /> Having to spend 64&nbsp;kBit to ''disable'' SRAM access seems like a waste considering a simple OR-gate could have stopped SRAM access.<br /> <br /> == Separate MBC1 Mode #WE ==<br /> <br /> The MBC1 Mode #WE stands out as being separated from mapping logic. Instead, if its #WE is not deasserted, it can be freely written even in mapped mode. However, the address line multiplexing for 16&nbsp;Mbit and 4&nbsp;Mbit does not switch with the mode setting -- which given a fixed ROM/SRAM wiring on the cartridge -- would need to be done in order for a hypothetical 16&nbsp;Mbit/256&nbsp;kBit mode to be feasible.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MMM01 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(6 downto 0);<br /> RA : out std_logic_vector(22 downto 14);<br /> AA : out std_logic_vector(16 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MMM01;<br /> <br /> architecture Behavioral of MMM01 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal ram_bank_we_n_r : std_logic_vector(1 downto 0);<br /> signal latch_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_r : std_logic_vector(8 downto 0);<br /> signal ram_bank_r : std_logic_vector(3 downto 0);<br /> signal mode_we_n_r : std_logic_vector(6 downto 6);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> signal rom_bank_we_n_r : std_logic_vector(4 downto 1);<br /> signal mux_r : std_logic_vector(0 downto 0);<br /> <br /> signal ra_int : std_logic_vector(4 downto 0);<br /> signal aa_int : std_logic_vector(1 downto 0);<br /> <br /> signal ra_lo : std_logic_vector(4 downto 0);<br /> signal ra_mask : std_logic_vector(4 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> alias rom_bank_r_lo : std_logic_vector(4 downto 0) is rom_bank_r(4 downto 0);<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when (A(15) = '0' and RD_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> ra_lo <= "11110" when (latch_r = "0") else<br /> rom_bank_r_lo;<br /> <br /> ra_mask <= "11110" when (latch_r = "0") else<br /> rom_bank_we_n_r & "0";<br /> <br /> ra_int <= "00000" when (A(14) = '0') else<br /> ra_lo when ((ra_lo and not(ra_mask)) /= "00000") else<br /> "00001";<br /> <br /> aa_int <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r(1 downto 0);<br /> <br /> AA(16 downto 15) <= ram_bank_r(3 downto 2);<br /> AA(14 downto 13) <= aa_int when (mux_r = "0") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(22 downto 21) <= "11" when (latch_r = "0") else<br /> rom_bank_r(8 downto 7);<br /> <br /> RA(20 downto 19) <= "11" when (latch_r = "0") else<br /> aa_int when (mux_r = "1") else<br /> rom_bank_r(6 downto 5);<br /> <br /> RA(18 downto 14) <= (ra_lo and ra_mask) or (ra_int and not(ra_mask));<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> ram_bank_we_n_r <= "00";<br /> latch_r <= "0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> if (latch_r = "0") then<br /> ram_bank_we_n_r <= D(5 downto 4);<br /> latch_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r(6 downto 0) <= "0000000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r(0) <= D(0);<br /> <br /> for i in rom_bank_we_n_r'range loop<br /> if (rom_bank_we_n_r(i) = '0') then<br /> rom_bank_r_lo(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> rom_bank_r(6 downto 5) <= D(6 downto 5);<br /> end if;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "0000";<br /> rom_bank_r(8 downto 7) <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> for i in ram_bank_we_n_r'range loop<br /> if (ram_bank_we_n_r(i) = '0') then<br /> ram_bank_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "0") then<br /> ram_bank_r(3 downto 2) <= D(3 downto 2);<br /> rom_bank_r(8 downto 7) <= D(5 downto 4);<br /> mode_we_n_r <= D(6 downto 6);<br /> end if;<br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> rom_bank_we_n_r <= "0000";<br /> mux_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> for i in mode_we_n_r'range loop<br /> if (mode_we_n_r(i) = '0') then<br /> mode_r(i) <= D(i);<br /> end if;<br /> end loop;<br /> <br /> if (latch_r = "1") then<br /> rom_bank_we_n_r <= D(5 downto 2);<br /> mux_r <= D(6 downto 6);<br /> end if;<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=File:MMM01_Pinout.png&diff=111 File:MMM01 Pinout.png 2017-06-23T16:47:09Z

<p>Tauwasser: Pinout for Nintendo's MMM01.</p> <hr /> <div>Pinout for Nintendo's MMM01.</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MBC1&diff=110 MBC1 2017-06-22T19:20:43Z

<p>Tauwasser: Removed superfluous RESET_N check in RAM_CS_N. RESET_N asynchronously resets ram_enable_r anyway.</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MBC1 can be used to address up to 16&nbsp;Mbit of ROM and 256&nbsp;kbit of SRAM, depending on the mode MBC1 is set to.<br /> <br /> = Pinout =<br /> <br /> [[Image:MBC1 Pinout.png|center|x300px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |24<br /> |VCC<br /> |PWR<br /> |5V supply<br /> |-<br /> |12<br /> |GND<br /> |PWR<br /> |Ground supply<br /> |-<br /> |5&ndash;1<br /> |D4&ndash;D0<br /> |I<br /> |Data Bus<br /> |-<br /> |11<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |22<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |23<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |10<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |21&ndash;19<br /> |A15&ndash;A13<br /> |I<br /> |Address Bus<br /> |-<br /> |18&ndash;14<br /> |RA18&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |7&ndash;6<br /> |AA14&ndash;AA13<br /> |O<br /> |Upper ROM/RAM Address Lines<br /> |-<br /> |8<br /> |{{Overline|RAM_CS}}<br /> |O<br /> |Low-Active RAM Chip Select<br /> |-<br /> |9<br /> |RAM_CS<br /> |O<br /> |High-Active RAM Chip Select<br /> |-<br /> |13<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |}<br /> <br /> Footprint: SOP127P1200X225-24<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0x0000-0x1FFF</tt>: RAM Enable register<br /> * <tt>0x2000-0x3FFF</tt>: ROM Bank register<br /> * <tt>0x4000-0x5FFF</tt>: RAM Bank register<br /> * <tt>0x6000-0x7FFF</tt>: Mode register<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX XX XX XX D3 D2 D1 D0 0x00 @ reset<br /> \_________/<br /> \-------- RAM Enable<br /> <br /> </pre><br /> <br /> A value of 0x0A enables SRAM access, all other values disable SRAM access.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX XX XX D4 D3 D2 D1 D0 0x00 @ reset<br /> \____________/<br /> \-------- ROM Bank<br /> <br /> </pre><br /> <br /> ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA18&ndash;RA14.<br /> <br /> == RAM Bank Register ==<br /> <br /> <pre><br /> XX XX XX XX XX XX D1 D0 0x00 @ reset<br /> \___/<br /> \----- RAM Bank<br /> <br /> </pre><br /> <br /> RAM Bank selects which bank is mapped to 0xA000-0xBFFF when in mode 4&nbsp;MBit/256&nbsp;kbit. When in mode 16&nbsp;Mbit/64&nbsp;kbit, it can be used to select the upper two ROM address lines.<br /> <br /> == Mode Register ==<br /> <br /> <pre><br /> XX XX XX XX XX XX XX D0 0x00 @ reset<br /> \/<br /> \--- Mode<br /> <br /> </pre><br /> <br /> The mode bit switches between 16&nbsp;Mbit ROM/64&nbsp;kbit SRAM mode ('0') and 4&nbsp;Mbit ROM/256&nbsp;kbit SRAM mode ('1'). When in 16&nbsp;Mbit/64&nbsp;kbit mode, address lines AA14&ndash;AA13 switch according to A14. When in 4&nbsp;Mbit/256&nbsp;kbit mode, the upper address lines AA14&ndash;AA13 stay fixed regardless of A14.<br /> <br /> = Behavior =<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> <br /> entity MBC1 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A : in std_logic_vector(15 downto 13);<br /> D : in std_logic_vector(4 downto 0);<br /> RA : out std_logic_vector(18 downto 14);<br /> AA : out std_logic_vector(14 downto 13);<br /> ROM_CS_N : out std_logic;<br /> RAM_CS_N : out std_logic;<br /> RAM_CS : out std_logic<br /> );<br /> end entity MBC1;<br /> <br /> architecture Behavioral of MBC1 is<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal rom_bank_r : std_logic_vector(4 downto 0);<br /> signal ram_bank_r : std_logic_vector(1 downto 0);<br /> signal mode_r : std_logic_vector(0 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_bank_r_clk : std_logic;<br /> signal mode_r_clk : std_logic;<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> ROM_CS_N <= '0' when ((A(15) = '0' and RD_N = '0') or RESET_N = '0') else<br /> '1';<br /> <br /> RAM_CS_N <= '0' when (CS_N = '0' and A(14) = '0' and ram_enable_r = x"A") else<br /> '1';<br /> RAM_CS <= not RAM_CS_N;<br /> <br /> RA(18 downto 14) <= "00000" when (A(14) = '0' or RESET_N = '0') else<br /> rom_bank_r when (rom_bank_r /= "00000") else<br /> "00001";<br /> <br /> AA(14 downto 13) <= "00" when (A(14) = '0' and mode_r = "0") else<br /> ram_bank_r;<br /> <br /> ram_enable_r_clk <= '0' when (A = "000" and WR_N = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A = "001" and WR_N = '0') else<br /> '1';<br /> <br /> ram_bank_r_clk <= '0' when (A = "010" and WR_N = '0') else<br /> '1';<br /> <br /> mode_r_clk <= '0' when (A = "011" and WR_N = '0') else<br /> '1';<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D(3 downto 0);<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r <= "00000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r <= D;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_bank_p : process (<br /> RESET_N,<br /> ram_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_bank_r <= "00";<br /> <br /> elsif (rising_edge(ram_bank_r_clk)) then<br /> <br /> ram_bank_r <= D(1 downto 0);<br /> <br /> end if;<br /> <br /> end process ram_bank_p;<br /> <br /> mode_p : process (<br /> RESET_N,<br /> mode_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> mode_r <= "0";<br /> <br /> elsif (rising_edge(mode_r_clk)) then<br /> <br /> mode_r <= D(0 downto 0);<br /> <br /> end if;<br /> <br /> end process mode_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MBC2&diff=109 MBC2 2017-06-09T04:21:59Z

<p>Tauwasser: I/O supply pins also supply core logic</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MBC2 can be used to address up to 2&nbsp;Mbit of ROM and 512&times;4&nbsp;bit of internal RAM.<br /> <br /> = Pinout =<br /> <br /> [[Image:MBC2 Pinout.png|center|x300px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |I/O + logic 5V supply<br /> |-<br /> |14<br /> |GND<br /> |PWR<br /> |I/O + logic Ground supply<br /> |-<br /> |21<br /> |VCC_RAM<br /> |PWR<br /> |RAM supply<br /> |-<br /> |7<br /> |GND_RAM<br /> |PWR<br /> |RAM Ground supply<br /> |-<br /> |12&ndash;9<br /> |D3&ndash;D0<br /> |I/O<br /> |Data Bus<br /> |-<br /> |1<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |27<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |26<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |15<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |20, 22&ndash;25, 8, 6&ndash;2<br /> |A15&ndash;A14, A8&ndash;A0<br /> |I<br /> |Address Bus<br /> |-<br /> |16&ndash;19<br /> |RA17&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |13<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |}<br /> <br /> Footprint: SOP127P1200X225-24<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. VCC and VCC_RAM both supply RAM -- probably depending on VCC voltage.<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0b00-- ---0 ---- ----</tt>: RAM Enable register<br /> * <tt>0b00-- ---1 ---- ----</tt>: ROM Bank register<br /> <br /> Read-Write-Accessible Registers:<br /> * <tt>0b10-- ---a aaaa aaaa</tt>: Internal RAM<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX XX XX XX D3 D2 D1 D0 0x00 @ reset<br /> \_________/<br /> \-------- RAM Enable<br /> <br /> </pre><br /> <br /> A value of 0x0A enables RAM access, all other values disable RAM access.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX XX XX XX D3 D2 D1 D0 0x00 @ reset<br /> \_________/<br /> \-------- ROM Bank<br /> <br /> </pre><br /> <br /> ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA17&ndash;RA14.<br /> <br /> = Behavior =<br /> <br /> When both {{Overline|RD}} and {{Overline|WR}} are low, MBC2 will drive 0x00 on D3..D0. The same is true for the reset state ({{Overline|RESET}} asserted). Therefore I modeled the behavior as belonging to the internal SRAM.<br /> There might be a power-up bug with MBC2. Many games do not make use of 0xA000, maybe because there really is a problem at reset.<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> use IEEE.numeric_std.all;<br /> <br /> entity MBC2 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A_HI : in std_logic_vector(15 downto 14);<br /> A : in std_logic_vector(8 downto 0);<br /> D : inout std_logic_vector(3 downto 0);<br /> RA : out std_logic_vector(17 downto 14);<br /> ROM_CS_N : out std_logic<br /> );<br /> end entity MBC2;<br /> <br /> architecture Behavioral of MBC2 is<br /> <br /> type ram_type is array(natural range <>) of std_logic_vector(3 downto 0);<br /> <br /> signal ram : ram_type(0 to 511);<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal rom_bank_r : std_logic_vector(3 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_clk : std_logic;<br /> <br /> signal ram_cs_n : std_logic;<br /> <br /> signal A_HI_int : std_logic_vector(A_HI'range);<br /> signal A_int : std_logic_vector(A'range);<br /> <br /> signal RD_N_int : std_logic;<br /> signal WR_N_int : std_logic;<br /> signal CS_N_int : std_logic;<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> A_HI_int <= A_HI and RESET_N;<br /> A_int <= A and RESET_N;<br /> RD_N_int <= RD_N and RESET_N;<br /> WR_N_int <= WR_N and RESET_N;<br /> CS_N_int <= CS_N and RESET_N;<br /> <br /> ROM_CS_N <= '0' when (A_HI_int(15) = '0' and RD_N_int = '0') else<br /> '1';<br /> <br /> ram_cs_n <= '0' when ((CS_N_int = '0' and A_HI_int(14) = '0' and ram_enable_r = x"A") or RESET_N = '0') else<br /> '1';<br /> <br /> RA <= "0000" when (A_HI_int(14) = '0') else<br /> rom_bank_r when (rom_bank_r /= "0000") else<br /> "0001";<br /> <br /> ram_enable_r_clk <= '0' when (A_HI_int = "00" and A_int(8) = '0' and WR_N_int = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A_HI_int = "00" and A_int(8) = '1' and WR_N_int = '0') else<br /> '1';<br /> <br /> ram_clk <= not RD_N_int or WR_N_int or ram_cs_n;<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r <= "0000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r <= D;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_p : process (<br /> A_int,<br /> D,<br /> WR_N_int,<br /> RD_N_int,<br /> ram_cs_n,<br /> ram_clk<br /> )<br /> begin<br /> <br /> -- default tri-state<br /> D <= "ZZZZ";<br /> <br /> -- read<br /> if (ram_cs_n = '0' and RD_N_int = '0' and WR_N_int /= '0') then<br /> -- write deasserted<br /> D <= ram(to_integer(unsigned(A_int)));<br /> elsif (ram_cs_n = '0' and RD_N_int = '0') then<br /> -- read and write asserted<br /> D <= "0000";<br /> end if;<br /> <br /> -- write<br /> if (rising_edge(ram_clk)) then<br /> <br /> ram(to_integer(unsigned(A_int))) <= D;<br /> <br /> end if;<br /> <br /> end process ram_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=MBC2&diff=108 MBC2 2016-10-26T22:13:38Z

<p>Tauwasser: /* Behavior */ fix syntax error, fix rising_edge compound argument</p> <hr /> <div>__TOC__<br /> <br /> Nintendo's MBC2 can be used to address up to 2&nbsp;Mbit of ROM and 512&times;4&nbsp;bit of internal RAM.<br /> <br /> = Pinout =<br /> <br /> [[Image:MBC2 Pinout.png|center|x300px]]<br /> <br /> {| class="wikitable pintable" style="margin:1em auto; width: 66%;"<br /> !style="width: 10%;" | Pin No.<br /> !style="width: 20%;" | Name<br /> !style="width: 10%;" | Type<br /> !style="width: 60%;" | Comment<br /> |-<br /> |28<br /> |VCC<br /> |PWR<br /> |I/O 5V supply<br /> |-<br /> |14<br /> |GND<br /> |PWR<br /> |I/O Ground supply<br /> |-<br /> |21<br /> |VCC_RAM<br /> |PWR<br /> |RAM supply<br /> |-<br /> |7<br /> |GND_RAM<br /> |PWR<br /> |RAM Ground supply<br /> |-<br /> |12&ndash;9<br /> |D3&ndash;D0<br /> |I/O<br /> |Data Bus<br /> |-<br /> |1<br /> |{{Overline|RD}}<br /> |I<br /> |Low-Active Read Enable<br /> |-<br /> |27<br /> |{{Overline|WR}}<br /> |I<br /> |Low-Active Write Enable<br /> |-<br /> |26<br /> |{{Overline|CS}}<br /> |I<br /> |Low-Active Chip Select<br /> |-<br /> |15<br /> |{{Overline|RESET}}<br /> |I<br /> |Low-Active Asynchronous Reset<br /> |-<br /> |20, 22&ndash;25, 8, 6&ndash;2<br /> |A15&ndash;A14, A8&ndash;A0<br /> |I<br /> |Address Bus<br /> |-<br /> |16&ndash;19<br /> |RA17&ndash;RA14<br /> |O<br /> |Upper ROM Address Lines<br /> |-<br /> |13<br /> |{{Overline|ROM_CS}}<br /> |O<br /> |Low-Active ROM Chip Select<br /> |}<br /> <br /> Footprint: SOP127P1200X225-24<br /> <br /> Remarks: All I/O pins are protected via diodes to VCC/GND. VCC and VCC_RAM both supply RAM -- probably depending on VCC voltage.<br /> <br /> {{clear|both}}<br /> <br /> = Registers =<br /> <br /> Write-Accessible Registers:<br /> <br /> * <tt>0b00-- ---0 ---- ----</tt>: RAM Enable register<br /> * <tt>0b00-- ---1 ---- ----</tt>: ROM Bank register<br /> <br /> Read-Write-Accessible Registers:<br /> * <tt>0b10-- ---a aaaa aaaa</tt>: Internal RAM<br /> <br /> == RAM Enable Register ==<br /> <br /> <pre><br /> XX XX XX XX D3 D2 D1 D0 0x00 @ reset<br /> \_________/<br /> \-------- RAM Enable<br /> <br /> </pre><br /> <br /> A value of 0x0A enables RAM access, all other values disable RAM access.<br /> <br /> == ROM Bank Register ==<br /> <br /> <pre><br /> XX XX XX XX D3 D2 D1 D0 0x00 @ reset<br /> \_________/<br /> \-------- ROM Bank<br /> <br /> </pre><br /> <br /> ROM Bank selects which bank is mapped to 0x4000-0x7FFF. The written value is zero-adjusted before output on RA17&ndash;RA14.<br /> <br /> = Behavior =<br /> <br /> When both {{Overline|RD}} and {{Overline|WR}} are low, MBC2 will drive 0x00 on D3..D0. The same is true for the reset state ({{Overline|RESET}} asserted). Therefore I modeled the behavior as belonging to the internal SRAM.<br /> There might be a power-up bug with MBC2. Many games do not make use of 0xA000, maybe because there really is a problem at reset.<br /> <br /> <source lang="vhdl"><br /> library IEEE;<br /> use IEEE.std_logic_1164.all;<br /> use IEEE.numeric_std.all;<br /> <br /> entity MBC2 is<br /> Port(<br /> RESET_N : in std_logic;<br /> RD_N : in std_logic;<br /> WR_N : in std_logic;<br /> CS_N : in std_logic;<br /> A_HI : in std_logic_vector(15 downto 14);<br /> A : in std_logic_vector(8 downto 0);<br /> D : inout std_logic_vector(3 downto 0);<br /> RA : out std_logic_vector(17 downto 14);<br /> ROM_CS_N : out std_logic<br /> );<br /> end entity MBC2;<br /> <br /> architecture Behavioral of MBC2 is<br /> <br /> type ram_type is array(natural range <>) of std_logic_vector(3 downto 0);<br /> <br /> signal ram : ram_type(0 to 511);<br /> <br /> signal ram_enable_r : std_logic_vector(3 downto 0);<br /> signal rom_bank_r : std_logic_vector(3 downto 0);<br /> <br /> signal ram_enable_r_clk : std_logic;<br /> signal rom_bank_r_clk : std_logic;<br /> signal ram_clk : std_logic;<br /> <br /> signal ram_cs_n : std_logic;<br /> <br /> signal A_HI_int : std_logic_vector(A_HI'range);<br /> signal A_int : std_logic_vector(A'range);<br /> <br /> signal RD_N_int : std_logic;<br /> signal WR_N_int : std_logic;<br /> signal CS_N_int : std_logic;<br /> <br /> begin<br /> <br /> -----------------------------------------------------------------------<br /> -- Signal Assignments<br /> -----------------------------------------------------------------------<br /> <br /> A_HI_int <= A_HI and RESET_N;<br /> A_int <= A and RESET_N;<br /> RD_N_int <= RD_N and RESET_N;<br /> WR_N_int <= WR_N and RESET_N;<br /> CS_N_int <= CS_N and RESET_N;<br /> <br /> ROM_CS_N <= '0' when (A_HI_int(15) = '0' and RD_N_int = '0') else<br /> '1';<br /> <br /> ram_cs_n <= '0' when ((CS_N_int = '0' and A_HI_int(14) = '0' and ram_enable_r = x"A") or RESET_N = '0') else<br /> '1';<br /> <br /> RA <= "0000" when (A_HI_int(14) = '0') else<br /> rom_bank_r when (rom_bank_r /= "0000") else<br /> "0001";<br /> <br /> ram_enable_r_clk <= '0' when (A_HI_int = "00" and A_int(8) = '0' and WR_N_int = '0') else<br /> '1';<br /> <br /> rom_bank_r_clk <= '0' when (A_HI_int = "00" and A_int(8) = '1' and WR_N_int = '0') else<br /> '1';<br /> <br /> ram_clk <= not RD_N_int or WR_N_int or ram_cs_n;<br /> <br /> -----------------------------------------------------------------------<br /> -- Registers<br /> -----------------------------------------------------------------------<br /> <br /> ram_enable_p : process (<br /> RESET_N,<br /> ram_enable_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> ram_enable_r <= x"0";<br /> <br /> elsif (rising_edge(ram_enable_r_clk)) then<br /> <br /> ram_enable_r <= D;<br /> <br /> end if;<br /> <br /> end process ram_enable_p;<br /> <br /> rom_bank_p : process (<br /> RESET_N,<br /> rom_bank_r_clk<br /> )<br /> begin<br /> <br /> if (RESET_N = '0') then<br /> <br /> rom_bank_r <= "0000";<br /> <br /> elsif (rising_edge(rom_bank_r_clk)) then<br /> <br /> rom_bank_r <= D;<br /> <br /> end if;<br /> <br /> end process rom_bank_p;<br /> <br /> ram_p : process (<br /> A_int,<br /> D,<br /> WR_N_int,<br /> RD_N_int,<br /> ram_cs_n,<br /> ram_clk<br /> )<br /> begin<br /> <br /> -- default tri-state<br /> D <= "ZZZZ";<br /> <br /> -- read<br /> if (ram_cs_n = '0' and RD_N_int = '0' and WR_N_int /= '0') then<br /> -- write deasserted<br /> D <= ram(to_integer(unsigned(A_int)));<br /> elsif (ram_cs_n = '0' and RD_N_int = '0') then<br /> -- read and write asserted<br /> D <= "0000";<br /> end if;<br /> <br /> -- write<br /> if (rising_edge(ram_clk)) then<br /> <br /> ram(to_integer(unsigned(A_int))) <= D;<br /> <br /> end if;<br /> <br /> end process ram_p;<br /> <br /> end architecture Behavioral;<br /> </source><br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Game_Boy_PCB_List&diff=107 Game Boy PCB List 2016-05-30T12:18:23Z

<p>Tauwasser: cat DMG</p> <hr /> <div>I distinguish between DMG PCBs and CGB PCBs, although obviously both kinds can be used in both hardware units. This distinction roughly corresponds to schedule 1 and schedule 2 PCBs licensed by Nintendo to 3rd parties like [http://www.sec.gov/Archives/edgar/containers/fix064/898441/000095000502000099/p14888ex10_33.txt 3DO] and [http://www.sec.gov/Archives/edgar/data/865570/000095015002001060/a85823exv10w4.txt THQ] and [http://www.sec.gov/Archives/edgar/containers/fix062/1132809/000095014801500958/v72115orex10-30.txt Bay Area Multimedia Inc. (BAM! Entertainment)].<br /> <br /> I don't own red carts, but know they exist.<br /> <br /> == DMG PCBs ==<br /> <br /> {| class="wikitable"<br /> ! Code!! MBC !! !! ROM !! !! RAM !!<br /> |-<br /> |AAA||||||256k||QFP80P1350X1350-44||||<br /> |-<br /> | style="color:red;" |AAAC||||||256k||COB?||||<br /> |-<br /> | BBA||MBC1||SOP127P1200X225-24||512k||QFP80P1350X1350-44||||<br /> |-<br /> | BCA||MBC1||SOP127P1200X225-24||1M||QFP80P1350X1350-44||||<br /> |-<br /> | BEAN||MBC1||SOP127P1200X225-24||4M||SOP127P1440X280-32||||<br /> |-<br /> | BEAN-M11||MBC1||SOP127P1200X225-24||2M||COB||||<br /> |-<br /> | BEAN-M13||MBC1||SOP127P1200X225-24||4M||COB||||<br /> |-<br /> | BEAN-M14||MBC1||SOP127P1200X225-24||2M||COB||||<br /> |-<br /> | BFAN||MBC1||SOP127P1200X225-24||8M||SOP127P1440X280-32||||<br /> |-<br /> | M-BFAN||MBC1||SOP127P1200X225-24||8M||SOP127P1440X280-32||||<br /> |-<br /> | DECN||MBC1||SOP127P1200X225-24||4M||SOP127P1440X280-32||64k||SOP127P1200X260-28<br /> |-<br /> | DEDN||MBC1||SOP127P1200X225-24||4M||SOP127P1440X280-32||256k||SOP127P1200X260-28<br /> |-<br /> | DFCN||MBC1||SOP127P1200X225-24||8M||SOP127P1440X280-32||64k||SOP127P1200X260-28<br /> |-<br /> | MC-DFCN||MBC1||SOP127P1200X225-24||8M||SOP127P1440X280-32||64k||SOP127P1200X260-28<br /> |-<br /> | DGCU||MBC1||SOP127P1200X225-24||16M||TSOP80P1176-44; TSOP-II||64k||SOP127P1200X260-28<br /> |-<br /> | GDAN||MBC2||SOP127P1200X225-28||2M||SOP127P1440X280-32||||<br /> |-<br /> | KECN||MBC3 w/X||QFP80P900X900-32||8M||SOP127P1440X280-32||64k||SOP127P1194X280-28<br /> |-<br /> | KFCN||MBC3 w/ X||QFP80P900X900-32||8M||SOP127P1440X280-32||64k||SOP127P1194X280-28<br /> |-<br /> | KFDN||MBC3 w/ X||QFP80P900X900-32||8M||SOP127P1440X280-32||256k||SOP127P1194X315-28<br /> |-<br /> | KGDU||MBC3 w/ X||QFP80P900X900-32||16M||TSOP80P1176-44; TSOP-II||256k||SOP127P1180X285-28<br /> |-<br /> | LFDN||MBC3 w/o X||QFP80P900X900-32||8M||SOP127P1440X280-32||256k||SOP127P1194X315-28<br /> |-<br /> | MHEU||MBC30 w/ X||TQFP80P900X900-32||32M||TSOP80P1176-44; TSOP-II||1M as 512k||SOP127P1410X305-32<br /> |-<br /> | M-PEAN||MMM01||QFP80P900X900-32||4M||SOP127P1440X280-32|||<br /> |-<br /> | M161-M01||74HC161A||SOP127P600X175-16||2M||SOP127P1440X280-32||||<br /> |-<br /> | M161-M12||74HC161A||SOP127P600X175-16||2M||COB||||<br /> |-<br /> | MC-SFCN||MMM01||QFP80P900X900-32||8M||SOP127P1440X280-32||64k||SOP127P1180X285-28<br /> |-<br /> | MMM-BEAN-M11||MMM01||QFP80P900X900-32||4M||COB||||<br /> |-<br /> | MMM-BEAN-M13||MMM01||QFP80P900X900-32||8M||COB||||<br /> |-<br /> | TEDN||HuC1A||QFP80P900X900-32||4M||SOP127P1440X280-32||256k||SOP127P1194X315-28<br /> |-<br /> | TFDN||HuC1||QFP80P900X900-32||8M||SOP127P1440X280-32||256k||SOP127P1194X315-28<br /> |-<br /> | UEDT||HuC3||QFP50P900X900-48||4M||TSOP50P1440-32; TSOP-I||256k||TSOP55P1340-28; TSOP-I<br /> |-<br /> | UFDT||HuC3||QFP50P900X900-48||8M||TSOP50P1440-32; TSOP-I||256k||TSOP55P1340-28; TSOP-I<br /> |-<br /> | UGDU||HuC3||QFP50P900X900-48||16M||TSOP80P1176-44; TSOP-II||256k||TSOP55P1340-28; TSOP-I<br /> |-<br /> | DMG-AOMJ||TAMA5||SOP127P1200X300-28||512k||SOP127P1440X290-32||||<br /> |-<br /> | MGB-MGBD||MAC-GBD||QFP50P1600X1600-100||8M||TSOP50P1440-32; TSOP-I||1M||TSOP50P1340-32; TSOP-I<br /> |}<br /> <br /> == CGB PCBs ==<br /> <br /> {| class="wikitable"<br /> ! Code!!MBC!!!!ROM!!!!RAM!!!!FLASH!!<br /> |-<br /> | A02||MBC5||QFP80P900X900-32||2/4/8M||SOP127P1440X280-32||256k||SOP127P1200X260-28||||<br /> |-<br /> | A03||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||256k||SOP127P1180X285-28||||<br /> |-<br /> | A04||MBC5||QFP80P900X900-32||4/8M||TSOP50P1440-32; TSOP-I||64k||SOP127P1200X260-28||||<br /> |-<br /> | A06||MBC5||QFP80P900X900-32||4/8M||SOP127P1440X280-32||64k||SOP127P1200X260-28||||<br /> |-<br /> | A07||MBC5||QFP80P900X900-32||2/4/8M||SOP127P1440X280-32||||||||<br /> |-<br /> | A08||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||64k||SOP127P1180X285-28||||<br /> |-<br /> | A09||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||||||||<br /> |-<br /> | A10||MBC5||QFP80P900X900-32||4/8M||TSOP50P1440-32; TSOP-I||||||||<br /> |-<br /> | A11||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||64k||SOP127P1180X285-28||||<br /> |-<br /> | A12||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||256k||SOP127P1194X315-28||||<br /> |-<br /> | A13||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||||||||<br /> |-<br /> | A14||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||1M||SOP127P1410X305-32||||<br /> |-<br /> | A15||MBC5||QFP80P900X900-32||2x32M||TSOP80P1176-44; TSOP-II||256k||SOP127P1180X285-28||||<br /> |-<br /> | A16||MBC5||QFP80P900X900-32||2/4/8M||SOP127P1440X280-32||1M||SOP127P1410X305-32||||<br /> |-<br /> | A18||MBC5||QFP80P900X900-32||16M||SOP127P1603X300-44||||||||<br /> |-<br /> | A20||G-MMC1||QFP40P1200X1200-80||||||1M||SOP127P1410X300-32||8M||TSOP50P2000-40<br /> |-<br /> | A32||MBC6||TQFP65P1400X1400-64||2/4/8M||SOP127P1440X280-32||256k||SOP127P1180X285-28||8M||TSOP50P2000-40<br /> |-<br /> | A40||MBC7||QFP65P1250X1250-56||4/8M||SOP127P1440X280-32||||||||<br /> |-<br /> | A47||MBC7||QFP65P1250X1250-56||16/32M||TSOP80P1176-44; TSOP-II||||||||<br /> |-<br /> | Z01||MBC5||QFP80P900X900-32||32M||TSOP80P1176-44; TSOP-II||64k||SOP127P1180X285-28||||<br /> |-<br /> | Z02||MBC5||QFP80P900X900-32||2/4/8M||SOP127P1440X280-32||256k as 64k||SOP127P1200X260-28||||<br /> |-<br /> | Z03||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||256k as 64k||SOP127P1200X260-28||||<br /> |-<br /> | Z04||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||256k as 64k||SOP127P1194X315-28||||<br /> |-<br /> | style="color:red;" | B02||Altera CPLD||||8/16/32M||||1M||||||<br /> |-<br /> | B03-01||Altera CPLD||||16/32M||TSOP50P2000X119-56; TSOP-II||256k||TSOP50P1340-32; TSOP-I||||<br /> |-<br /> | B03-11||MBC5-D||QFP80P1350X1350-44||16/32M||TSOP50P2000X119-56; TSOP-II||256k||TSOP50P1340-32; TSOP-I||||<br /> |-<br /> | style="color:red;" |B04||MBC5-D||||64M||||1M||||||<br /> |-<br /> | style="color:red;" |F01||?||||32/64M||||||||||<br /> |}<br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Game_Boy_PCB_List&diff=106 Game Boy PCB List 2016-05-30T11:46:08Z

<p>Tauwasser: Create List from Excel</p> <hr /> <div>I distinguish between DMG PCBs and CGB PCBs, although obviously both kinds can be used in both hardware units. This distinction roughly corresponds to schedule 1 and schedule 2 PCBs licensed by Nintendo to 3rd parties like [http://www.sec.gov/Archives/edgar/containers/fix064/898441/000095000502000099/p14888ex10_33.txt 3DO] and [http://www.sec.gov/Archives/edgar/data/865570/000095015002001060/a85823exv10w4.txt THQ] and [http://www.sec.gov/Archives/edgar/containers/fix062/1132809/000095014801500958/v72115orex10-30.txt Bay Area Multimedia Inc. (BAM! Entertainment)].<br /> <br /> == DMG PCBs ==<br /> <br /> {| class="wikitable"<br /> ! Code!! MBC !! !! ROM !! !! RAM !!<br /> |-<br /> | AAA||||||256k||QFP80P1350X1350-44||||<br /> |-<br /> | AAAC||||||256k||COB?||||<br /> |-<br /> | BBA||MBC1||SOP127P1200X225-24||512k||QFP80P1350X1350-44||||<br /> |-<br /> | BCA||MBC1||SOP127P1200X225-24||1M||QFP80P1350X1350-44||||<br /> |-<br /> | BEAN||MBC1||SOP127P1200X225-24||4M||SOP127P1440X280-32||||<br /> |-<br /> | BEAN-M11||MBC1||SOP127P1200X225-24||2M||COB||||<br /> |-<br /> | BEAN-M13||MBC1||SOP127P1200X225-24||4M||COB||||<br /> |-<br /> | BEAN-M14||MBC1||SOP127P1200X225-24||2M||COB||||<br /> |-<br /> | BFAN||MBC1||SOP127P1200X225-24||8M||SOP127P1440X280-32||||<br /> |-<br /> | M-BFAN||MBC1||SOP127P1200X225-24||8M||SOP127P1440X280-32||||<br /> |-<br /> | DECN||MBC1||SOP127P1200X225-24||4M||SOP127P1440X280-32||64k||SOP127P1200X260-28<br /> |-<br /> | DEDN||MBC1||SOP127P1200X225-24||4M||SOP127P1440X280-32||256k||SOP127P1200X260-28<br /> |-<br /> | DFCN||MBC1||SOP127P1200X225-24||8M||SOP127P1440X280-32||64k||SOP127P1200X260-28<br /> |-<br /> | MC-DFCN||MBC1||SOP127P1200X225-24||8M||SOP127P1440X280-32||64k||SOP127P1200X260-28<br /> |-<br /> | DGCU||MBC1||SOP127P1200X225-24||16M||TSOP80P1176-44; TSOP-II||64k||SOP127P1200X260-28<br /> |-<br /> | GDAN||MBC2||SOP127P1200X225-28||2M||SOP127P1440X280-32||||<br /> |-<br /> | KECN||MBC3 w/X||QFP80P900X900-32||8M||SOP127P1440X280-32||64k||SOP127P1194X280-28<br /> |-<br /> | KFCN||MBC3 w/ X||QFP80P900X900-32||8M||SOP127P1440X280-32||64k||SOP127P1194X280-28<br /> |-<br /> | KFDN||MBC3 w/ X||QFP80P900X900-32||8M||SOP127P1440X280-32||256k||SOP127P1194X315-28<br /> |-<br /> | KGDU||MBC3 w/ X||QFP80P900X900-32||16M||TSOP80P1176-44; TSOP-II||256k||SOP127P1180X285-28<br /> |-<br /> | LFDN||MBC3 w/o X||QFP80P900X900-32||8M||SOP127P1440X280-32||256k||SOP127P1194X315-28<br /> |-<br /> | MHEU||MBC30 w/ X||TQFP80P900X900-32||32M||TSOP80P1176-44; TSOP-II||1M as 512k||SOP127P1410X305-32<br /> |-<br /> | M-PEAN||MMM01||QFP80P900X900-32||4M||SOP127P1440X280-32|||<br /> |-<br /> | M161-M01||74HC161A||SOP127P600X175-16||2M||SOP127P1440X280-32||||<br /> |-<br /> | M161-M12||74HC161A||SOP127P600X175-16||2M||COB||||<br /> |-<br /> | MC-SFCN||MMM01||QFP80P900X900-32||8M||SOP127P1440X280-32||64k||SOP127P1180X285-28<br /> |-<br /> | MMM-BEAN-M11||MMM01||QFP80P900X900-32||4M||COB||||<br /> |-<br /> | MMM-BEAN-M13||MMM01||QFP80P900X900-32||8M||COB||||<br /> |-<br /> | TEDN||HuC1A||QFP80P900X900-32||4M||SOP127P1440X280-32||256k||SOP127P1194X315-28<br /> |-<br /> | TFDN||HuC1||QFP80P900X900-32||8M||SOP127P1440X280-32||256k||SOP127P1194X315-28<br /> |-<br /> | UEDT||HuC3||QFP50P900X900-48||4M||TSOP50P1440-32; TSOP-I||256k||TSOP55P1340-28; TSOP-I<br /> |-<br /> | UFDT||HuC3||QFP50P900X900-48||8M||TSOP50P1440-32; TSOP-I||256k||TSOP55P1340-28; TSOP-I<br /> |-<br /> | UGDU||HuC3||QFP50P900X900-48||16M||TSOP80P1176-44; TSOP-II||256k||TSOP55P1340-28; TSOP-I<br /> |-<br /> | DMG-AOMJ||TAMA5||SOP127P1200X300-28||512k||SOP127P1440X290-32||||<br /> |-<br /> | MGB-MGBD||MAC-GBD||QFP50P1600X1600-100||8M||TSOP50P1440-32; TSOP-I||1M||TSOP50P1340-32; TSOP-I<br /> |}<br /> <br /> == CGB PCBs ==<br /> <br /> {| class="wikitable"<br /> ! Code!!MBC!!!!ROM!!!!RAM!!!!FLASH!!<br /> |-<br /> | A02||MBC5||QFP80P900X900-32||2/4/8M||SOP127P1440X280-32||256k||SOP127P1200X260-28||||<br /> |-<br /> | A03||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||256k||SOP127P1180X285-28||||<br /> |-<br /> | A04||MBC5||QFP80P900X900-32||4/8M||TSOP50P1440-32; TSOP-I||64k||SOP127P1200X260-28||||<br /> |-<br /> | A06||MBC5||QFP80P900X900-32||4/8M||SOP127P1440X280-32||64k||SOP127P1200X260-28||||<br /> |-<br /> | A07||MBC5||QFP80P900X900-32||2/4/8M||SOP127P1440X280-32||||||||<br /> |-<br /> | A08||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||64k||SOP127P1180X285-28||||<br /> |-<br /> | A09||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||||||||<br /> |-<br /> | A10||MBC5||QFP80P900X900-32||4/8M||TSOP50P1440-32; TSOP-I||||||||<br /> |-<br /> | A11||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||64k||SOP127P1180X285-28||||<br /> |-<br /> | A12||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||256k||SOP127P1194X315-28||||<br /> |-<br /> | A13||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||||||||<br /> |-<br /> | A14||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||1M||SOP127P1410X305-32||||<br /> |-<br /> | A15||MBC5||QFP80P900X900-32||2x32M||TSOP80P1176-44; TSOP-II||256k||SOP127P1180X285-28||||<br /> |-<br /> | A16||MBC5||QFP80P900X900-32||2/4/8M||SOP127P1440X280-32||1M||SOP127P1410X305-32||||<br /> |-<br /> | A18||MBC5||QFP80P900X900-32||16M||SOP127P1603X300-44||||||||<br /> |-<br /> | A20||G-MMC1||QFP40P1200X1200-80||||||1M||SOP127P1410X300-32||8M||TSOP50P2000-40<br /> |-<br /> | A32||MBC6||TQFP65P1400X1400-64||2/4/8M||SOP127P1440X280-32||256k||SOP127P1180X285-28||8M||TSOP50P2000-40<br /> |-<br /> | A40||MBC7||QFP65P1250X1250-56||4/8M||SOP127P1440X280-32||||||||<br /> |-<br /> | A47||MBC7||QFP65P1250X1250-56||16/32M||TSOP80P1176-44; TSOP-II||||||||<br /> |-<br /> | Z01||MBC5||QFP80P900X900-32||32M||TSOP80P1176-44; TSOP-II||64k||SOP127P1180X285-28||||<br /> |-<br /> | Z02||MBC5||QFP80P900X900-32||2/4/8M||SOP127P1440X280-32||256k as 64k||SOP127P1200X260-28||||<br /> |-<br /> | Z03||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||256k as 64k||SOP127P1200X260-28||||<br /> |-<br /> | Z04||MBC5||QFP80P900X900-32||16/32/64M||TSOP80P1176-44; TSOP-II||256k as 64k||SOP127P1194X315-28||||<br /> |-<br /> | B02||Altera CPLD||||8/16/32M||||1M||||||<br /> |-<br /> | B03||MBC5-D||QFP80P1350X1350-44||16/32M||TSOP50P2000X119-56; TSOP-II||256k||TSOP50P1340-32; TSOP-I||||<br /> |-<br /> | B04||MBC5-D||||64M||||1M||||||<br /> |-<br /> | F01||?||||32/64M||||||||||<br /> |}</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Game_Boy_Naming_Convention&diff=105 Game Boy Naming Convention 2016-05-30T10:58:51Z

<p>Tauwasser: some changes and additions thanks to Gekkio</p> <hr /> <div>= DMG PCB Naming Convention =<br /> <br /> DMG PCB codes follow the following convention:<br /> <br /> DMG[-?[?]]-???[?][(?)]-NN<br /> | | | \-- PCB revision<br /> | | \------- optional code in parentheses<br /> | \-------------- mandatory three or four-letter descriptor<br /> \--------------------- one or two-letter optional part<br /> <br /> == Descriptor Codes ==<br /> <br /> {| class="wikitable sortable"<br /> |-<br /> ! Code<br /> ! scope="col" class="unsortable" |MBC/Battery<br /> ! scope="col" class="unsortable" |ROM Size<br /> ! scope="col" class="unsortable" |RAM Size<br /> ! scope="col" class="unsortable" |ROM Package<br /> |-<br /> | (none)<br /> | -<br /> | -<br /> | -<br /> | QFP<br /> |-<br /> | A<br /> | none<br /> | 256kbit<br /> | none<br /> | -<br /> |-<br /> | B<br /> | MBC1A/MBC1B/MBC1B1<br /> | 512kbit<br /> | -?<br /> | -<br /> |-<br /> | C<br /> | -<br /> | 1Mbit<br /> | 64kbit<br /> | COB<br /> |-<br /> | D<br /> | MBC1A/MBC1B/MBC1B1 + CR1616<br /> | 2Mbit<br /> | 256kbit<br /> | -<br /> |-<br /> | E<br /> | -<br /> | 4Mbit<br /> | 512kbit<br /> | -<br /> |-<br /> | F<br /> | -<br /> | 8Mbit<br /> | -<br /> | -<br /> |-<br /> | G<br /> | MBC2A + CR1616<br /> | 16Mbit<br /> | -<br /> | -<br /> |-<br /> | H<br /> | -<br /> | 32Mbit<br /> | -<br /> | -<br /> |-<br /> | K<br /> | MBC3/MBC3A/MBC3B w/ X + CR2025<br /> | -<br /> | -<br /> | -<br /> |-<br /> | L<br /> | MBC3/MBC3A/MBC3B w/o X + CR2025<br /> | -<br /> | -<br /> | -<br /> |-<br /> | M<br /> | MBC30 w/ X + CR2025<br /> | -<br /> | -<br /> | -<br /> |-<br /> | N<br /> | -<br /> | -<br /> | -<br /> | SOP<br /> |-<br /> | P<br /> | MMM01<br /> | -<br /> | -<br /> | -<br /> |-<br /> | S<br /> | MMM01 + CR1616<br /> | -<br /> | -<br /> | -<br /> |-<br /> | T<br /> | HuC1/HuC1A + CR1616<br /> | -<br /> | -<br /> | TSOP I<br /> |-<br /> | U<br /> | HuC3A + CR2025<br /> | -<br /> | -<br /> | TSOP II<br /> |}<br /> <br /> For example, DMG-BEAN-02 is a PCB made for<br /> * MBC1A/MBC1B/MBC1B1 (without battery)<br /> * 256kbit of ROM<br /> * no SRAM<br /> * ROM chip package is a narrow SOIC (SOP)<br /> <br /> ROM and RAM sizes are maximum sizes, i.e. smaller memories will alias, while bigger memories will be inaccessible past the stated size.<br /> <br /> == PCB Revisions ==<br /> <br /> Numbers include<br /> <br /> *01<br /> *02<br /> *03<br /> *10<br /> *20<br /> *SP<br /> <br /> Mostly minor routing differences if any. Sometimes additional components in 10, 20, SP.<br /> First figure is major revision -- i.e. additional components, bigger changes -- while second figure is minor changes in masks only.<br /> <br /> == Optional Parts ==<br /> <br /> * DMG-MC-SFCN-01 Momotarou Collection 2<br /> * DMG-M-PEAN-10 Taito Variety Pack<br /> <br /> MC = Momotarou Collection? MultiCart?<br /> <br /> Code in parentheses after descriptor is only ever K.<br /> <br /> * DMG-BEAN(K)-10 Xenon 2<br /> * DMG-DECN(K)-02 Mogurania (Mole Mania)<br /> <br /> Working hypothesis: PCBs were made in Korea and to track failure rates, marked with (K)?<br /> <br /> = CGB PCB Naming Convention =<br /> <br /> CGB PCB codes follow the following convention:<br /> <br /> DMG-?NN-NN<br /> ||| \-- PCB revision<br /> ||\----- PCB descriptor RAM/ROM size combination<br /> |\------ PCB descriptor MBC<br /> \------- PCB code<br /> <br /> == PCB Code ==<br /> <br /> *A: Production Cartridges<br /> *B: Test Cartridges<br /> *Z: Revisions of certain A?? variants. Sometimes routing changes.<br /> <br /> == PCB Descriptor ==<br /> <br /> Descriptors describe MBC and ROM/RAM size combinations only.<br /> <br /> {| class="wikitable sortable"<br /> |-<br /> ! rowspan="2" |Number<br /> ! scope="col" class="unsortable" rowspan="2" |MBC<br /> ! scope="col" class="unsortable" colspan="2" |RAM/ROM size combination<br /> |-<br /> ! RAM sizes<br /> ! ROM sizes<br /> |-<br /> | 0<br /> | MBC5 (w/ or w/o rumble)<br /> | 4/8M<br /> | 2/4k EEPROM or 1M SRAM<br /> |-<br /> | 1<br /> | MBC5 (w/ rumble)<br /> | 16/32/64M<br /> | 64k<br /> |-<br /> | 2<br /> | G-MMC1 (+ 8M FLASH)<br /> | 2/4/8M<br /> | 256k<br /> |-<br /> | 3<br /> | MBC6 (+ 8M FLASH)<br /> | 16/32/64M<br /> | 256k<br /> |-<br /> | 4<br /> | MBC7<br /> | 4/8M<br /> | -?<br /> |-<br /> | 5<br /> | -<br /> | -?<br /> | -?<br /> |-<br /> | 6<br /> | -<br /> | 2/4/8M<br /> | 64k<br /> |-<br /> | 7<br /> | -<br /> | 16/32M<br /> | 2/4k EEPROM<br /> |-<br /> | 8<br /> | -<br /> | -?<br /> | -?<br /> |-<br /> | 9<br /> | -<br /> | -?<br /> | -?<br /> |}<br /> <br /> Maybe actually hierarchy? I.e. second figure is sub-index in first figure MBC PCB designs?<br /> <br /> == PCB Revisions ==<br /> <br /> Numbers include<br /> <br /> *01<br /> *10<br /> <br /> Never observed any major differences. Maybe minor solder mask differences?<br /> <br /> [[Category:DMG]]</div>

Tauwasser https://wiki.tauwasser.eu/index.php?title=Game_Boy_Dumping_Misc&diff=104 Game Boy Dumping Misc 2016-04-23T12:02:21Z

<p>Tauwasser: cat</p> <hr /> <div>== Nikkan Berutomo Club ==<br /> <br /> Nikkan Berutomo Club (Japan) (SGB Enhanced) might be a bad dump. Name entry screen katakana contains ロ (katakana RO) twice, ル (katakana RU) is missing in right-most column.<br /> Change 2:5163 to 0x83 to rectify this. Might indicate fixed global checksum and possibly other bad bits/bytes. Or maybe the original developers just forgot?<br /> <br /> <gallery widths=160px heights=144px><br /> DMG_Nikkan_Berutomo_Club_Name_Entry_Before.png|Before<br /> DMG_Nikkan_Berutomo_Club_Name_Entry_After.png|After<br /> </gallery><br /> <br /> [[Category:DMG]]</div>

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